Factorize vqshrnbq, vqshrntq, vqrshrnbq, vqrshrntq, vshrntq, vshrnbq,
vrshrnbq and vrshrntq so that they use the same pattern.
Introduce <isu> iterator for *shrn* so that we can use the same
pattern despite the different "s", "u" and "i" suffixes.
2022-09-08 Christophe Lyon <christophe.l...@arm.com>
gcc/
* config/arm/iterators.md (MVE_SHRN_N, MVE_SHRN_M_N): New.
(mve_insn): Add vqrshrnb, vqrshrnt, vqshrnb, vqshrnt, vrshrnb,
vrshrnt, vshrnb, vshrnt.
(isu): New.
* config/arm/mve.md (mve_vqrshrnbq_n_<supf><mode>)
(mve_vqrshrntq_n_<supf><mode>, mve_vqshrnbq_n_<supf><mode>)
(mve_vqshrntq_n_<supf><mode>, mve_vrshrnbq_n_<supf><mode>)
(mve_vrshrntq_n_<supf><mode>, mve_vshrnbq_n_<supf><mode>)
(mve_vshrntq_n_<supf><mode>): Merge into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vqrshrnbq_m_n_<supf><mode>, mve_vqrshrntq_m_n_<supf><mode>)
(mve_vqshrnbq_m_n_<supf><mode>, mve_vqshrntq_m_n_<supf><mode>)
(mve_vrshrnbq_m_n_<supf><mode>, mve_vrshrntq_m_n_<supf><mode>)
(mve_vshrnbq_m_n_<supf><mode>, mve_vshrntq_m_n_<supf><mode>):
Merge into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
---
gcc/config/arm/iterators.md | 57 ++++++++
gcc/config/arm/mve.md | 270 ++++--------------------------------
2 files changed, 85 insertions(+), 242 deletions(-)
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 9ff61e0573b..d64c924a513 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -468,6 +468,28 @@ (define_int_iterator MVE_RSHIFT_N [
VRSHLQ_N_S VRSHLQ_N_U
])
+(define_int_iterator MVE_SHRN_N [
+ VQRSHRNBQ_N_S VQRSHRNBQ_N_U
+ VQRSHRNTQ_N_S VQRSHRNTQ_N_U
+ VQSHRNBQ_N_S VQSHRNBQ_N_U
+ VQSHRNTQ_N_S VQSHRNTQ_N_U
+ VRSHRNBQ_N_S VRSHRNBQ_N_U
+ VRSHRNTQ_N_S VRSHRNTQ_N_U
+ VSHRNBQ_N_S VSHRNBQ_N_U
+ VSHRNTQ_N_S VSHRNTQ_N_U
+ ])
+
+(define_int_iterator MVE_SHRN_M_N [
+ VQRSHRNBQ_M_N_S VQRSHRNBQ_M_N_U
+ VQRSHRNTQ_M_N_S VQRSHRNTQ_M_N_U
+ VQSHRNBQ_M_N_S VQSHRNBQ_M_N_U
+ VQSHRNTQ_M_N_S VQSHRNTQ_M_N_U
+ VRSHRNBQ_M_N_S VRSHRNBQ_M_N_U
+ VRSHRNTQ_M_N_S VRSHRNTQ_M_N_U
+ VSHRNBQ_M_N_S VSHRNBQ_M_N_U
+ VSHRNTQ_M_N_S VSHRNTQ_M_N_U
+ ])
+
(define_int_iterator MVE_FP_M_BINARY [
VABDQ_M_F
VADDQ_M_F
@@ -568,12 +590,20 @@ (define_int_attr mve_insn [
(VQRSHLQ_M_S "vqrshl") (VQRSHLQ_M_U "vqrshl")
(VQRSHLQ_N_S "vqrshl") (VQRSHLQ_N_U "vqrshl")
(VQRSHLQ_S "vqrshl") (VQRSHLQ_U "vqrshl")
+ (VQRSHRNBQ_M_N_S "vqrshrnb") (VQRSHRNBQ_M_N_U "vqrshrnb")
+ (VQRSHRNBQ_N_S "vqrshrnb") (VQRSHRNBQ_N_U "vqrshrnb")
+ (VQRSHRNTQ_M_N_S "vqrshrnt") (VQRSHRNTQ_M_N_U "vqrshrnt")
+ (VQRSHRNTQ_N_S "vqrshrnt") (VQRSHRNTQ_N_U "vqrshrnt")
(VQSHLQ_M_N_S "vqshl") (VQSHLQ_M_N_U "vqshl")
(VQSHLQ_M_R_S "vqshl") (VQSHLQ_M_R_U "vqshl")
(VQSHLQ_M_S "vqshl") (VQSHLQ_M_U "vqshl")
(VQSHLQ_N_S "vqshl") (VQSHLQ_N_U "vqshl")
(VQSHLQ_R_S "vqshl") (VQSHLQ_R_U "vqshl")
(VQSHLQ_S "vqshl") (VQSHLQ_U "vqshl")
+ (VQSHRNBQ_M_N_S "vqshrnb") (VQSHRNBQ_M_N_U "vqshrnb")
+ (VQSHRNBQ_N_S "vqshrnb") (VQSHRNBQ_N_U "vqshrnb")
+ (VQSHRNTQ_M_N_S "vqshrnt") (VQSHRNTQ_M_N_U "vqshrnt")
+ (VQSHRNTQ_N_S "vqshrnt") (VQSHRNTQ_N_U "vqshrnt")
(VQSUBQ_M_N_S "vqsub") (VQSUBQ_M_N_U "vqsub")
(VQSUBQ_M_S "vqsub") (VQSUBQ_M_U "vqsub")
(VQSUBQ_N_S "vqsub") (VQSUBQ_N_U "vqsub")
@@ -586,17 +616,44 @@ (define_int_attr mve_insn [
(VRSHLQ_M_S "vrshl") (VRSHLQ_M_U "vrshl")
(VRSHLQ_N_S "vrshl") (VRSHLQ_N_U "vrshl")
(VRSHLQ_S "vrshl") (VRSHLQ_U "vrshl")
+ (VRSHRNBQ_M_N_S "vrshrnb") (VRSHRNBQ_M_N_U "vrshrnb")
+ (VRSHRNBQ_N_S "vrshrnb") (VRSHRNBQ_N_U "vrshrnb")
+ (VRSHRNTQ_M_N_S "vrshrnt") (VRSHRNTQ_M_N_U "vrshrnt")
+ (VRSHRNTQ_N_S "vrshrnt") (VRSHRNTQ_N_U "vrshrnt")
(VSHLQ_M_N_S "vshl") (VSHLQ_M_N_U "vshl")
(VSHLQ_M_R_S "vshl") (VSHLQ_M_R_U "vshl")
(VSHLQ_M_S "vshl") (VSHLQ_M_U "vshl")
(VSHLQ_N_S "vshl") (VSHLQ_N_U "vshl")
(VSHLQ_R_S "vshl") (VSHLQ_R_U "vshl")
(VSHLQ_S "vshl") (VSHLQ_U "vshl")
+ (VSHRNBQ_M_N_S "vshrnb") (VSHRNBQ_M_N_U "vshrnb")
+ (VSHRNBQ_N_S "vshrnb") (VSHRNBQ_N_U "vshrnb")
+ (VSHRNTQ_M_N_S "vshrnt") (VSHRNTQ_M_N_U "vshrnt")
+ (VSHRNTQ_N_S "vshrnt") (VSHRNTQ_N_U "vshrnt")
(VSUBQ_M_N_S "vsub") (VSUBQ_M_N_U "vsub") (VSUBQ_M_N_F "vsub")
(VSUBQ_M_S "vsub") (VSUBQ_M_U "vsub") (VSUBQ_M_F "vsub")
(VSUBQ_N_S "vsub") (VSUBQ_N_U "vsub") (VSUBQ_N_F "vsub")
])
+(define_int_attr isu [
+ (VQRSHRNBQ_M_N_S "s") (VQRSHRNBQ_M_N_U "u")
+ (VQRSHRNBQ_N_S "s") (VQRSHRNBQ_N_U "u")
+ (VQRSHRNTQ_M_N_S "s") (VQRSHRNTQ_M_N_U "u")
+ (VQRSHRNTQ_N_S "s") (VQRSHRNTQ_N_U "u")
+ (VQSHRNBQ_M_N_S "s") (VQSHRNBQ_M_N_U "u")
+ (VQSHRNBQ_N_S "s") (VQSHRNBQ_N_U "u")
+ (VQSHRNTQ_M_N_S "s") (VQSHRNTQ_M_N_U "u")
+ (VQSHRNTQ_N_S "s") (VQSHRNTQ_N_U "u")
+ (VRSHRNBQ_M_N_S "i") (VRSHRNBQ_M_N_U "i")
+ (VRSHRNBQ_N_S "i") (VRSHRNBQ_N_U "i")
+ (VRSHRNTQ_M_N_S "i") (VRSHRNTQ_M_N_U "i")
+ (VRSHRNTQ_N_S "i") (VRSHRNTQ_N_U "i")
+ (VSHRNBQ_M_N_S "i") (VSHRNBQ_M_N_U "i")
+ (VSHRNBQ_N_S "i") (VSHRNBQ_N_U "i")
+ (VSHRNTQ_M_N_S "i") (VSHRNTQ_M_N_U "i")
+ (VSHRNTQ_N_S "i") (VSHRNTQ_N_U "i")
+ ])
+
;; plus and minus are the only SHIFTABLE_OPS for which Thumb2 allows
;; a stack pointer operand. The minus operation is a candidate for an rsub
;; and hence only plus is supported.
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 44409b40e5f..d64a075c7bb 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -2162,21 +2162,30 @@ (define_insn "mve_vcvtq_m_to_f_<supf><mode>"
"vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem> %q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
+
;;
-;; [vqrshrnbq_n_u, vqrshrnbq_n_s])
+;; [vqrshrnbq_n_u, vqrshrnbq_n_s]
+;; [vqrshrntq_n_u, vqrshrntq_n_s]
+;; [vqshrnbq_n_u, vqshrnbq_n_s]
+;; [vqshrntq_n_u, vqshrntq_n_s]
+;; [vrshrnbq_n_s, vrshrnbq_n_u]
+;; [vrshrntq_n_u, vrshrntq_n_s]
+;; [vshrnbq_n_u, vshrnbq_n_s]
+;; [vshrntq_n_s, vshrntq_n_u]
;;
-(define_insn "mve_vqrshrnbq_n_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_n_<supf><mode>"
[
(set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
(unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1
"s_register_operand" "0")
(match_operand:MVE_5 2 "s_register_operand"
"w")
(match_operand:SI 3 "<MVE_pred3>"
"<MVE_constraint3>")]
- VQRSHRNBQ_N))
+ MVE_SHRN_N))
]
"TARGET_HAVE_MVE"
- "vqrshrnb.<supf>%#<V_sz_elem> %q0, %q2, %3"
+ "<mve_insn>.<isu>%#<V_sz_elem>\t%q0, %q2, %3"
[(set_attr "type" "mve_move")
])
+
;;
;; [vqrshrunbq_n_s])
;;
@@ -2192,6 +2201,7 @@ (define_insn "mve_vqrshrunbq_n_s<mode>"
"vqrshrunb.s%#<V_sz_elem>\t%q0, %q2, %3"
[(set_attr "type" "mve_move")
])
+
;;
;; [vrmlaldavhaq_s vrmlaldavhaq_u])
;;
@@ -3992,22 +4002,6 @@ (define_insn "mve_vqmovuntq_m_s<mode>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vqrshrntq_n_u, vqrshrntq_n_s])
-;;
-(define_insn "mve_vqrshrntq_n_<supf><mode>"
- [
- (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
- (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1
"s_register_operand" "0")
- (match_operand:MVE_5 2 "s_register_operand" "w")
- (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
- VQRSHRNTQ_N))
- ]
- "TARGET_HAVE_MVE"
- "vqrshrnt.<supf>%#<V_sz_elem> %q0, %q2, %3"
- [(set_attr "type" "mve_move")
-])
-
;;
;; [vqrshruntq_n_s])
;;
@@ -4024,38 +4018,6 @@ (define_insn "mve_vqrshruntq_n_s<mode>"
[(set_attr "type" "mve_move")
])
-;;
-;; [vqshrnbq_n_u, vqshrnbq_n_s])
-;;
-(define_insn "mve_vqshrnbq_n_<supf><mode>"
- [
- (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
- (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1
"s_register_operand" "0")
- (match_operand:MVE_5 2 "s_register_operand" "w")
- (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
- VQSHRNBQ_N))
- ]
- "TARGET_HAVE_MVE"
- "vqshrnb.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vqshrntq_n_u, vqshrntq_n_s])
-;;
-(define_insn "mve_vqshrntq_n_<supf><mode>"
- [
- (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
- (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1
"s_register_operand" "0")
- (match_operand:MVE_5 2 "s_register_operand" "w")
- (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
- VQSHRNTQ_N))
- ]
- "TARGET_HAVE_MVE"
- "vqshrnt.<supf>%#<V_sz_elem> %q0, %q2, %3"
- [(set_attr "type" "mve_move")
-])
-
;;
;; [vqshrunbq_n_s])
;;
@@ -4296,70 +4258,6 @@ (define_insn "mve_vrndxq_m_f<mode>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vrshrnbq_n_s, vrshrnbq_n_u])
-;;
-(define_insn "mve_vrshrnbq_n_<supf><mode>"
- [
- (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
- (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1
"s_register_operand" "0")
- (match_operand:MVE_5 2 "s_register_operand" "w")
- (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
- VRSHRNBQ_N))
- ]
- "TARGET_HAVE_MVE"
- "vrshrnb.i%#<V_sz_elem> %q0, %q2, %3"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vrshrntq_n_u, vrshrntq_n_s])
-;;
-(define_insn "mve_vrshrntq_n_<supf><mode>"
- [
- (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
- (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1
"s_register_operand" "0")
- (match_operand:MVE_5 2 "s_register_operand" "w")
- (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
- VRSHRNTQ_N))
- ]
- "TARGET_HAVE_MVE"
- "vrshrnt.i%#<V_sz_elem> %q0, %q2, %3"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vshrnbq_n_u, vshrnbq_n_s])
-;;
-(define_insn "mve_vshrnbq_n_<supf><mode>"
- [
- (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
- (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1
"s_register_operand" "0")
- (match_operand:MVE_5 2 "s_register_operand" "w")
- (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
- VSHRNBQ_N))
- ]
- "TARGET_HAVE_MVE"
- "vshrnb.i%#<V_sz_elem> %q0, %q2, %3"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vshrntq_n_s, vshrntq_n_u])
-;;
-(define_insn "mve_vshrntq_n_<supf><mode>"
- [
- (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
- (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1
"s_register_operand" "0")
- (match_operand:MVE_5 2 "s_register_operand"
"w")
- (match_operand:SI 3 "<MVE_pred3>"
"<MVE_constraint3>")]
- VSHRNTQ_N))
- ]
- "TARGET_HAVE_MVE"
- "vshrnt.i%#<V_sz_elem>\t%q0, %q2, %3"
- [(set_attr "type" "mve_move")
-])
-
;;
;; [vcvtmq_m_s, vcvtmq_m_u])
;;
@@ -4992,70 +4890,26 @@ (define_insn "mve_vmlaldavaxq_p_<supf><mode>"
(set_attr "length""8")])
;;
-;; [vqrshrnbq_m_n_u, vqrshrnbq_m_n_s])
-;;
-(define_insn "mve_vqrshrnbq_m_n_<supf><mode>"
- [
- (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
- (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1
"s_register_operand" "0")
- (match_operand:MVE_5 2 "s_register_operand" "w")
- (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VQRSHRNBQ_M_N))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vqrshrnbt.<supf>%#<V_sz_elem> %q0, %q2, %3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vqrshrntq_m_n_s, vqrshrntq_m_n_u])
-;;
-(define_insn "mve_vqrshrntq_m_n_<supf><mode>"
- [
- (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
- (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1
"s_register_operand" "0")
- (match_operand:MVE_5 2 "s_register_operand" "w")
- (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VQRSHRNTQ_M_N))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vqrshrntt.<supf>%#<V_sz_elem> %q0, %q2, %3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vqshrnbq_m_n_u, vqshrnbq_m_n_s])
-;;
-(define_insn "mve_vqshrnbq_m_n_<supf><mode>"
- [
- (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
- (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1
"s_register_operand" "0")
- (match_operand:MVE_5 2 "s_register_operand" "w")
- (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VQSHRNBQ_M_N))
- ]
- "TARGET_HAVE_MVE"
- "vpst\n\tvqshrnbt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vqshrntq_m_n_s, vqshrntq_m_n_u])
+;; [vqrshrnbq_m_n_u, vqrshrnbq_m_n_s]
+;; [vqrshrntq_m_n_s, vqrshrntq_m_n_u]
+;; [vqshrnbq_m_n_u, vqshrnbq_m_n_s]
+;; [vqshrntq_m_n_s, vqshrntq_m_n_u]
+;; [vrshrnbq_m_n_u, vrshrnbq_m_n_s]
+;; [vrshrntq_m_n_u, vrshrntq_m_n_s]
+;; [vshrnbq_m_n_s, vshrnbq_m_n_u]
+;; [vshrntq_m_n_s, vshrntq_m_n_u]
;;
-(define_insn "mve_vqshrntq_m_n_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
[
(set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
(unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1
"s_register_operand" "0")
- (match_operand:MVE_5 2 "s_register_operand" "w")
- (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VQSHRNTQ_M_N))
+ (match_operand:MVE_5 2 "s_register_operand"
"w")
+ (match_operand:SI 3 "<MVE_pred3>"
"<MVE_constraint3>")
+ (match_operand:<MVE_VPRED> 4
"vpr_register_operand" "Up")]
+ MVE_SHRN_M_N))
]
"TARGET_HAVE_MVE"
- "vpst\;vqshrntt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
+ "vpst\;<mve_insn>t.<isu>%#<V_sz_elem>\t%q0, %q2, %3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -5076,40 +4930,6 @@ (define_insn "mve_vrmlaldavhaq_p_sv4si"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vrshrnbq_m_n_u, vrshrnbq_m_n_s])
-;;
-(define_insn "mve_vrshrnbq_m_n_<supf><mode>"
- [
- (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
- (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1
"s_register_operand" "0")
- (match_operand:MVE_5 2 "s_register_operand" "w")
- (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VRSHRNBQ_M_N))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vrshrnbt.i%#<V_sz_elem>\t%q0, %q2, %3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vrshrntq_m_n_u, vrshrntq_m_n_s])
-;;
-(define_insn "mve_vrshrntq_m_n_<supf><mode>"
- [
- (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
- (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1
"s_register_operand" "0")
- (match_operand:MVE_5 2 "s_register_operand" "w")
- (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VRSHRNTQ_M_N))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vrshrntt.i%#<V_sz_elem>\t%q0, %q2, %3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vshllbq_m_n_u, vshllbq_m_n_s])
;;
@@ -5144,40 +4964,6 @@ (define_insn "mve_vshlltq_m_n_<supf><mode>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vshrnbq_m_n_s, vshrnbq_m_n_u])
-;;
-(define_insn "mve_vshrnbq_m_n_<supf><mode>"
- [
- (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
- (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1
"s_register_operand" "0")
- (match_operand:MVE_5 2 "s_register_operand" "w")
- (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VSHRNBQ_M_N))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vshrnbt.i%#<V_sz_elem>\t%q0, %q2, %3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vshrntq_m_n_s, vshrntq_m_n_u])
-;;
-(define_insn "mve_vshrntq_m_n_<supf><mode>"
- [
- (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
- (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1
"s_register_operand" "0")
- (match_operand:MVE_5 2 "s_register_operand" "w")
- (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VSHRNTQ_M_N))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vshrntt.i%#<V_sz_elem>\t%q0, %q2, %3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vmlsldavaq_p_s])
;;
--
2.34.1
