From: Juzhe-Zhong <juzhe.zh...@rivai.ai>
This incorrect codes blocks the scalable RVV auto-vectorization.
Take a look at this target hook implementation of aarch64.
They only have the similiar handling on TARGET_SIMD.
They let movmisalign<mode> to handle scalable vector of SVE.
For RVV, we should follow the same implementation of ARM SVE.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_support_vector_misalignment): Fix
incorrect codes.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/v-2.c: Adapt testcase.
* gcc.target/riscv/rvv/autovec/zve32f-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve32f-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve32x-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve32x-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64d-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64d-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64f-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64f-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64x-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64x-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c: Ditto.
---
gcc/config/riscv/riscv.cc | 21 +++++++------------
.../gcc.target/riscv/rvv/autovec/v-2.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/zve32f-2.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/zve32f-3.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/zve32x-2.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/zve32x-3.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zve64d-2.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/zve64d-3.c | 4 ++--
.../riscv/rvv/autovec/zve64d_zvl128b-2.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/zve64f-2.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/zve64f-3.c | 4 ++--
.../riscv/rvv/autovec/zve64f_zvl128b-2.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/zve64x-2.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/zve64x-3.c | 2 +-
.../riscv/rvv/autovec/zve64x_zvl128b-2.c | 2 +-
15 files changed, 32 insertions(+), 39 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 8684271f8ac..ff90c44d811 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7264,27 +7264,20 @@ riscv_estimated_poly_value (poly_int64 val,
return val.coeffs[0] + val.coeffs[1] * over_128 / 128;
}
+/* Return true if the vector misalignment factor is supported by the
+ target. */
bool
riscv_support_vector_misalignment (machine_mode mode,
const_tree type ATTRIBUTE_UNUSED,
int misalignment,
bool is_packed ATTRIBUTE_UNUSED)
{
- if (TARGET_VECTOR)
- {
- if (STRICT_ALIGNMENT)
- {
- /* Return if movmisalign pattern is not supported for this mode. */
- if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing)
- return false;
-
- /* Misalignment factor is unknown at compile time. */
- if (misalignment == -1)
- return false;
- }
- return true;
- }
+ /* TODO: For RVV scalable vector auto-vectorization, we should allow
+ movmisalign<mode> pattern to handle misalign data movement to unblock
+ possible auto-vectorization.
+ RVV VLS auto-vectorization or SIMD auto-vectorization can be supported
here
+ in the future. */
return default_builtin_support_vector_misalignment (mode, type, misalignment,
is_packed);
}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c
index 3d086e30081..66d8ea15f5b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d --param
riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-vect-cost-model --param
riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
#include "template-1.h"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect"
} } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 6 "vect"
} } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c
index d6199665126..7cdc174c06f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d --param
riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -fno-vect-cost-model
--param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
#include "template-1.h"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 1 "vect"
} } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect"
} } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c
index d5109c72045..5654a34ea5c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d --param
riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2
-fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -fno-vect-cost-model
--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2
-fdump-tree-vect-details" } */
#include "template-1.h"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect"
} } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect"
} } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c
index 575e9479f94..1602f5f17d7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d --param
riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -fno-vect-cost-model
--param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
#include "template-1.h"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 1 "vect"
} } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect"
} } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c
index 50e8963033b..5cc8f1462d6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d --param
riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2
-fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -fno-vect-cost-model
--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2
-fdump-tree-vect-details" } */
#include "template-1.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c
index 0d6ebc53d1a..5e38b41a5c3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d --param
riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -fno-vect-cost-model
--param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
#include "template-1.h"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 1 "vect"
} } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect"
} } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c
index 2a72030c3bc..6a23713d1ce 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d --param
riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2
-fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -fno-vect-cost-model
--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2
-fdump-tree-vect-details" } */
#include "template-1.h"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect"
} } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 6 "vect"
} } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c
index 9e236e0af1b..20429967f36 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d --param
riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d
-fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax
-fdump-tree-vect-details" } */
#include "template-1.h"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect"
} } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 6 "vect"
} } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c
index 6bb6b919c77..ee37282f1f8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d --param
riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -fno-vect-cost-model
--param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
#include "template-1.h"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 1 "vect"
} } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect"
} } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c
index 43eca9d0727..a4618e00494 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d --param
riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2
-fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -fno-vect-cost-model
--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2
-fdump-tree-vect-details" } */
#include "template-1.h"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect"
} } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect"
} } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c
index f1500074370..64caef5c6ef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d --param
riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d
-fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax
-fdump-tree-vect-details" } */
#include "template-1.h"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect"
} } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect"
} } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c
index ede28e88dac..6a64a1a1fdf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d --param
riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -fno-vect-cost-model
--param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
#include "template-1.h"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 1 "vect"
} } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect"
} } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c
index d59f7362b43..a30e73371ce 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d --param
riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2
-fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -fno-vect-cost-model
--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2
-fdump-tree-vect-details" } */
#include "template-1.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c
index 90398db52a0..b98a8704276 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d --param
riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d
-fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax
-fdump-tree-vect-details" } */
#include "template-1.h"
--
2.36.3
