Factorize vmaxnmq and vminnmq so that they use the same pattern.
2022-09-08 Christophe Lyon <christophe.l...@arm.com>
gcc/
* config/arm/iterators.md (MAX_MIN_F): New.
(MVE_FP_M_BINARY): Add VMAXNMQ_M_F, VMINNMQ_M_F.
(mve_insn): Add vmaxnm, vminnm.
(max_min_f_str): New.
* config/arm/mve.md (mve_vmaxnmq_f<mode>, mve_vminnmq_f<mode>):
Merge into ...
(@mve_<max_min_f_str>q_f<mode>): ... this.
(mve_vmaxnmq_m_f<mode>, mve_vminnmq_m_f<mode>): Merge into ...
(@mve_<mve_insn>q_m_f<mode>): ... this.
---
gcc/config/arm/iterators.md | 10 ++++++
gcc/config/arm/mve.md | 63 ++++++-------------------------------
2 files changed, 19 insertions(+), 54 deletions(-)
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 5bb7e2be7c8..397ac32720d 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -333,6 +333,9 @@ (define_code_iterator SSPLUSMINUS [ss_plus ss_minus])
;; Max/Min iterator, to factorize MVE patterns
(define_code_iterator MAX_MIN_SU [smax umax smin umin])
+;; Floating-point Max/Min iterator, to factorize MVE patterns
+(define_code_iterator MAX_MIN_F [smax smin])
+
;; MVE integer unary operations.
(define_int_iterator MVE_INT_M_UNARY [
VABSQ_M_S
@@ -547,6 +550,8 @@ (define_int_iterator MVE_SHRN_M_N [
(define_int_iterator MVE_FP_M_BINARY [
VABDQ_M_F
VADDQ_M_F
+ VMAXNMQ_M_F
+ VMINNMQ_M_F
VMULQ_M_F
VSUBQ_M_F
])
@@ -643,11 +648,13 @@ (define_int_attr mve_insn [
(VHSUBQ_S "vhsub") (VHSUBQ_U "vhsub")
(VMAXAVQ_P_S "vmaxav")
(VMAXAVQ_S "vmaxav")
+ (VMAXNMQ_M_F "vmaxnm")
(VMAXQ_M_S "vmax") (VMAXQ_M_U "vmax")
(VMAXVQ_P_S "vmaxv") (VMAXVQ_P_U "vmaxv")
(VMAXVQ_S "vmaxv") (VMAXVQ_U "vmaxv")
(VMINAVQ_P_S "vminav")
(VMINAVQ_S "vminav")
+ (VMINNMQ_M_F "vminnm")
(VMINQ_M_S "vmin") (VMINQ_M_U "vmin")
(VMINVQ_P_S "vminv") (VMINVQ_P_U "vminv")
(VMINVQ_S "vminv") (VMINVQ_U "vminv")
@@ -1516,6 +1523,9 @@ (define_code_attr max_min_supf [
(smin "s") (umin "u")
])
+;; Floating-point max/min for MVE
+(define_code_attr max_min_f_str [(smax "vmaxnm") (smin "vminnm")])
+
;;----------------------------------------------------------------------------
;; Int attributes
;;----------------------------------------------------------------------------
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 715e85c9998..d2863b316e0 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -1455,16 +1455,17 @@ (define_insn "mve_vmaxnmavq_f<mode>"
])
;;
-;; [vmaxnmq_f])
+;; [vmaxnmq_f]
+;; [vminnmq_f]
;;
-(define_insn "mve_vmaxnmq_f<mode>"
+(define_insn "@mve_<max_min_f_str>q_f<mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (smax:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")
- (match_operand:MVE_0 2 "s_register_operand" "w")))
+ (MAX_MIN_F:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")
+ (match_operand:MVE_0 2 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vmaxnm.f%#<V_sz_elem> %q0, %q1, %q2"
+ "<max_min_f_str>.f%#<V_sz_elem> %q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
@@ -1513,20 +1514,6 @@ (define_insn "mve_vminnmavq_f<mode>"
[(set_attr "type" "mve_move")
])
-;;
-;; [vminnmq_f])
-;;
-(define_insn "mve_vminnmq_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (smin:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")
- (match_operand:MVE_0 2 "s_register_operand" "w")))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vminnm.f%#<V_sz_elem> %q0, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
;;
;; [vminnmvq_f])
;;
@@ -4533,8 +4520,10 @@ (define_insn "mve_vrmlsldavhaxq_p_sv4si"
;;
;; [vabdq_m_f]
;; [vaddq_m_f]
-;; [vsubq_m_f]
+;; [vmaxnmq_m_f]
+;; [vminnmq_m_f]
;; [vmulq_m_f]
+;; [vsubq_m_f]
;;
(define_insn "@mve_<mve_insn>q_m_f<mode>"
[
@@ -4844,40 +4833,6 @@ (define_insn "mve_vfmsq_m_f<mode>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vmaxnmq_m_f])
-;;
-(define_insn "mve_vmaxnmq_m_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
- (match_operand:MVE_0 2 "s_register_operand" "w")
- (match_operand:MVE_0 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VMAXNMQ_M_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vmaxnmt.f%#<V_sz_elem> %q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vminnmq_m_f])
-;;
-(define_insn "mve_vminnmq_m_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
- (match_operand:MVE_0 2 "s_register_operand" "w")
- (match_operand:MVE_0 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VMINNMQ_M_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vminnmt.f%#<V_sz_elem> %q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vornq_m_f])
;;
--
2.34.1
