Address comments. Thanks.
juzhe.zh...@rivai.ai From: Philipp Tomsich Date: 2023-05-15 16:21 To: juzhe.zhong CC: gcc-patches; kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc Subject: Re: [PATCH] RISC-V: Add rounding mode operand for fixed-point patterns On Mon, 15 May 2023 at 10:18, <juzhe.zh...@rivai.ai> wrote: > > From: Juzhe-Zhong <juzhe.zh...@rivai.ai> > > Since we are going to have fixed-point intrinsics that are modeling rounding > mode > https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/222 > > We should have operand to specify rounding mode in fixed-point instructions. > We don't support these modeling rounding mode intrinsics yet but we will > definetely > support them later. > > This is the preparing patch for new coming intrinsics. > > gcc/ChangeLog: > > * config/riscv/riscv-protos.h (enum vxrm_field_enum): New enum. > * config/riscv/riscv-vector-builtins.cc > (function_expander::use_exact_insn): Add default rounding mode operand. > * config/riscv/riscv.cc (riscv_hard_regno_nregs): Add VXRM_RENUM. > (riscv_hard_regno_mode_ok): Ditto. > (riscv_conditional_register_usage): Ditto. > * config/riscv/riscv.h (DWARF_FRAME_REGNUM): Ditto. > (VXRM_REG_P): Ditto. > (RISCV_DWARF_VXRM): Ditto. > * config/riscv/riscv.md: Ditto. > * config/riscv/vector.md: Ditto. > > --- > gcc/config/riscv/riscv-protos.h | 8 +++ > gcc/config/riscv/riscv-vector-builtins.cc | 7 +++ > gcc/config/riscv/riscv.cc | 5 +- > gcc/config/riscv/riscv.h | 5 +- > gcc/config/riscv/riscv.md | 1 + > gcc/config/riscv/vector.md | 74 +++++++++++++++++------ > 6 files changed, 77 insertions(+), 23 deletions(-) > > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h > index bc71f9cbbba..835bb802fc6 100644 > --- a/gcc/config/riscv/riscv-protos.h > +++ b/gcc/config/riscv/riscv-protos.h > @@ -223,6 +223,14 @@ machine_mode preferred_simd_mode (scalar_mode); > opt_machine_mode get_mask_mode (machine_mode); > void expand_vec_series (rtx, rtx, rtx); > void expand_vec_init (rtx, rtx); > +/* Rounding mode bitfield for fixed point VXRM. */ > +enum vxrm_field_enum > +{ > + VXRM_RNU, > + VXRM_RNE, > + VXRM_RDN, > + VXRM_ROD > +}; > } > > /* We classify builtin types into two classes: > diff --git a/gcc/config/riscv/riscv-vector-builtins.cc > b/gcc/config/riscv/riscv-vector-builtins.cc > index 0f56f29f7aa..1de075fb90d 100644 > --- a/gcc/config/riscv/riscv-vector-builtins.cc > +++ b/gcc/config/riscv/riscv-vector-builtins.cc > @@ -3288,6 +3288,13 @@ function_expander::use_exact_insn (insn_code icode) > > if (base->apply_vl_p ()) > add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX)); > + > + /* TODO: Currently, we don't support intrinsic that is modeling rounding > mode. > + We add default rounding mode for the intrinsics that didn't model > rounding > + mode yet. */ > + if (opno != insn_data[icode].n_generator_args) > + add_input_operand (Pmode, const0_rtx); > + > return generate_insn (icode); > } > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index a770fdfaa0e..c9c8861f84a 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -6082,7 +6082,7 @@ riscv_hard_regno_nregs (unsigned int regno, > machine_mode mode) > > /* mode for VL or VTYPE are just a marker, not holding value, > so it always consume one register. */ > - if (regno == VTYPE_REGNUM || regno == VL_REGNUM) > + if (regno == VTYPE_REGNUM || regno == VL_REGNUM || regno == VXRM_REGNUM) Shouldn't this be VXRM_REG_P(...), VTYPE_REG_P(...), and VL_REG_P(...)? > return 1; > > /* Assume every valid non-vector mode fits in one vector register. */ > @@ -6150,7 +6150,7 @@ riscv_hard_regno_mode_ok (unsigned int regno, > machine_mode mode) > if (lmul != 1) > return ((regno % lmul) == 0); > } > - else if (regno == VL_REGNUM || regno == VTYPE_REGNUM) > + else if (regno == VL_REGNUM || regno == VTYPE_REGNUM || regno == > VXRM_REGNUM) Ditto. > return true; > else > return false; > @@ -6586,6 +6586,7 @@ riscv_conditional_register_usage (void) > > fixed_regs[VTYPE_REGNUM] = call_used_regs[VTYPE_REGNUM] = 1; > fixed_regs[VL_REGNUM] = call_used_regs[VL_REGNUM] = 1; > + fixed_regs[VXRM_REGNUM] = call_used_regs[VXRM_REGNUM] = 1; > } > } > > diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h > index 4473115d3a9..f74b70de562 100644 > --- a/gcc/config/riscv/riscv.h > +++ b/gcc/config/riscv/riscv.h > @@ -121,7 +121,8 @@ ASM_MISA_SPEC > > /* The mapping from gcc register number to DWARF 2 CFA column number. */ > #define DWARF_FRAME_REGNUM(REGNO) > \ > - (VL_REG_P (REGNO) ? RISCV_DWARF_VL > \ > + (VXRM_REG_P (REGNO) ? RISCV_DWARF_VXRM > \ > + : VL_REG_P (REGNO) ? RISCV_DWARF_VL > \ > : VTYPE_REG_P (REGNO) > \ > ? RISCV_DWARF_VTYPE > \ > : (GP_REG_P (REGNO) || FP_REG_P (REGNO) || V_REG_P (REGNO) > \ > @@ -372,6 +373,7 @@ ASM_MISA_SPEC > ((unsigned int) ((int) (REGNO) - V_REG_FIRST) < V_REG_NUM) > #define VL_REG_P(REGNO) ((REGNO) == VL_REGNUM) > #define VTYPE_REG_P(REGNO) ((REGNO) == VTYPE_REGNUM) > +#define VXRM_REG_P(REGNO) ((REGNO) == VXRM_REGNUM) > > /* True when REGNO is in SIBCALL_REGS set. */ > #define SIBCALL_REG_P(REGNO) \ > @@ -390,6 +392,7 @@ ASM_MISA_SPEC > #define FRAME_POINTER_REGNUM 65 > > /* Define Dwarf for RVV. */ > +#define RISCV_DWARF_VXRM (4096 + 0x00a) > #define RISCV_DWARF_VL (4096 + 0xc20) > #define RISCV_DWARF_VTYPE (4096 + 0xc21) > #define RISCV_DWARF_VLENB (4096 + 0xc22) > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > index 7065e68c0b7..c5cf3af9868 100644 > --- a/gcc/config/riscv/riscv.md > +++ b/gcc/config/riscv/riscv.md > @@ -135,6 +135,7 @@ > (EXCEPTION_RETURN 2) > (VL_REGNUM 66) > (VTYPE_REGNUM 67) > + (VXRM_REGNUM 68) > ]) > > (include "predicates.md") > diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md > index 328fce8d632..db3e120d97c 100644 > --- a/gcc/config/riscv/vector.md > +++ b/gcc/config/riscv/vector.md > @@ -3317,8 +3317,10 @@ > (match_operand 6 "const_int_operand" " i, i, i, i, > i, i, i, i") > (match_operand 7 "const_int_operand" " i, i, i, i, > i, i, i, i") > (match_operand 8 "const_int_operand" " i, i, i, i, > i, i, i, i") > + (match_operand 9 "const_int_operand" " i, > i, i, i, i, i, i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE) > (any_sat_int_binop:VI > (match_operand:VI 3 "<binop_rhs1_predicate>" " vr, vr, vr, vr, > vr, vr, vr, vr") > (match_operand:VI 4 "<binop_rhs2_predicate>" > "<binop_rhs2_constraint>")) > @@ -3346,8 +3348,10 @@ > (match_operand 6 "const_int_operand" " i, i, i, i") > (match_operand 7 "const_int_operand" " i, i, i, i") > (match_operand 8 "const_int_operand" " i, i, i, i") > + (match_operand 9 "const_int_operand" " i, > i, i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE) > (sat_int_plus_binop:VI_QHS > (vec_duplicate:VI_QHS > (match_operand:<VEL> 4 "register_operand" " r, r, r, r")) > @@ -3367,8 +3371,10 @@ > (match_operand 6 "const_int_operand" " i, i, i, i") > (match_operand 7 "const_int_operand" " i, i, i, i") > (match_operand 8 "const_int_operand" " i, i, i, i") > + (match_operand 9 "const_int_operand" " i, > i, i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE) > (sat_int_minus_binop:VI_QHS > (match_operand:VI_QHS 3 "register_operand" " vr, vr, vr, vr") > (vec_duplicate:VI_QHS > @@ -3388,8 +3394,10 @@ > (match_operand 6 "const_int_operand") > (match_operand 7 "const_int_operand") > (match_operand 8 "const_int_operand") > + (match_operand 9 "const_int_operand") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE) > (sat_int_plus_binop:VI_D > (vec_duplicate:VI_D > (match_operand:<VEL> 4 "reg_or_int_operand")) > @@ -3407,7 +3415,7 @@ > [] (rtx *operands, rtx boardcast_scalar) { > emit_insn (gen_pred_<optab><mode> (operands[0], operands[1], > operands[2], operands[3], boardcast_scalar, operands[5], > - operands[6], operands[7], operands[8])); > + operands[6], operands[7], operands[8], operands[9])); > })) > DONE; > }) > @@ -3421,8 +3429,10 @@ > (match_operand 6 "const_int_operand" " i, i, i, i") > (match_operand 7 "const_int_operand" " i, i, i, i") > (match_operand 8 "const_int_operand" " i, i, i, i") > + (match_operand 9 "const_int_operand" " i, > i, i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE) > (sat_int_plus_binop:VI_D > (vec_duplicate:VI_D > (match_operand:<VEL> 4 "register_operand" " r, r, r, r")) > @@ -3442,8 +3452,10 @@ > (match_operand 6 "const_int_operand" " i, i, i, > i") > (match_operand 7 "const_int_operand" " i, i, i, > i") > (match_operand 8 "const_int_operand" " i, i, i, > i") > + (match_operand 9 "const_int_operand" " > i, i, i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE) > (sat_int_plus_binop:VI_D > (vec_duplicate:VI_D > (sign_extend:<VEL> > @@ -3464,8 +3476,10 @@ > (match_operand 6 "const_int_operand") > (match_operand 7 "const_int_operand") > (match_operand 8 "const_int_operand") > + (match_operand 9 "const_int_operand") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE) > (sat_int_minus_binop:VI_D > (match_operand:VI_D 3 "register_operand") > (vec_duplicate:VI_D > @@ -3483,7 +3497,7 @@ > [] (rtx *operands, rtx boardcast_scalar) { > emit_insn (gen_pred_<optab><mode> (operands[0], operands[1], > operands[2], operands[3], boardcast_scalar, operands[5], > - operands[6], operands[7], operands[8])); > + operands[6], operands[7], operands[8], operands[9])); > })) > DONE; > }) > @@ -3497,8 +3511,10 @@ > (match_operand 6 "const_int_operand" " i, i, i, i") > (match_operand 7 "const_int_operand" " i, i, i, i") > (match_operand 8 "const_int_operand" " i, i, i, i") > + (match_operand 9 "const_int_operand" " i, > i, i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE) > (sat_int_minus_binop:VI_D > (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr") > (vec_duplicate:VI_D > @@ -3518,8 +3534,10 @@ > (match_operand 6 "const_int_operand" " i, i, i, > i") > (match_operand 7 "const_int_operand" " i, i, i, > i") > (match_operand 8 "const_int_operand" " i, i, i, > i") > + (match_operand 9 "const_int_operand" " > i, i, i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE) > (sat_int_minus_binop:VI_D > (match_operand:VI_D 3 "register_operand" " vr, vr, vr, > vr") > (vec_duplicate:VI_D > @@ -3540,8 +3558,10 @@ > (match_operand 6 "const_int_operand" " i, i, i, i") > (match_operand 7 "const_int_operand" " i, i, i, i") > (match_operand 8 "const_int_operand" " i, i, i, i") > + (match_operand 9 "const_int_operand" " i, > i, i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE) > (unspec:VI > [(match_operand:VI 3 "register_operand" " vr, vr, vr, vr") > (match_operand:VI 4 "register_operand" " vr, vr, vr, vr")] > VSAT_OP) > @@ -3561,8 +3581,10 @@ > (match_operand 6 "const_int_operand" " i, i, i, i") > (match_operand 7 "const_int_operand" " i, i, i, i") > (match_operand 8 "const_int_operand" " i, i, i, i") > + (match_operand 9 "const_int_operand" " i, > i, i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE) > (unspec:VI_QHS > [(match_operand:VI_QHS 3 "register_operand" " vr, vr, vr, vr") > (match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")] > VSAT_ARITH_OP) > @@ -3581,8 +3603,10 @@ > (match_operand 6 "const_int_operand" " i, i, i, i") > (match_operand 7 "const_int_operand" " i, i, i, i") > (match_operand 8 "const_int_operand" " i, i, i, i") > + (match_operand 9 "const_int_operand" " i, > i, i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE) > (unspec:VI > [(match_operand:VI 3 "register_operand" " vr, vr, vr, vr") > (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, > rK")] VSAT_SHIFT_OP) > @@ -3603,8 +3627,10 @@ > (match_operand 6 "const_int_operand") > (match_operand 7 "const_int_operand") > (match_operand 8 "const_int_operand") > + (match_operand 9 "const_int_operand") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE) > (unspec:VI_D > [(match_operand:VI_D 3 "register_operand") > (match_operand:<VEL> 4 "reg_or_int_operand")] VSAT_ARITH_OP) > @@ -3621,7 +3647,7 @@ > [] (rtx *operands, rtx boardcast_scalar) { > emit_insn (gen_pred_<sat_op><mode> (operands[0], operands[1], > operands[2], operands[3], boardcast_scalar, operands[5], > - operands[6], operands[7], operands[8])); > + operands[6], operands[7], operands[8], operands[9])); > })) > DONE; > }) > @@ -3635,8 +3661,10 @@ > (match_operand 6 "const_int_operand" " i, i, i, i") > (match_operand 7 "const_int_operand" " i, i, i, i") > (match_operand 8 "const_int_operand" " i, i, i, i") > + (match_operand 9 "const_int_operand" " i, > i, i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE) > (unspec:VI_D > [(match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr") > (match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")] > VSAT_ARITH_OP) > @@ -3655,8 +3683,10 @@ > (match_operand 6 "const_int_operand" " i, i, i, i") > (match_operand 7 "const_int_operand" " i, i, i, i") > (match_operand 8 "const_int_operand" " i, i, i, i") > + (match_operand 9 "const_int_operand" " i, > i, i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE) > (unspec:VI_D > [(match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr") > (sign_extend:<VEL> > @@ -3677,8 +3707,10 @@ > (match_operand 6 "const_int_operand" " i, > i, i, i, i, i, i, i, i, i, i, i") > (match_operand 7 "const_int_operand" " i, > i, i, i, i, i, i, i, i, i, i, i") > (match_operand 8 "const_int_operand" " i, > i, i, i, i, i, i, i, i, i, i, i") > + (match_operand 9 "const_int_operand" > " i, i, i, i, i, i, i, i, i, i, i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE) > (unspec:<V_DOUBLE_TRUNC> > [(match_operand:VWEXTI 3 "register_operand" " > vr,vr, vr, vr, 0, 0, vr, vr, 0, 0, vr, vr") > (match_operand:<V_DOUBLE_TRUNC> 4 "vector_shift_operand" " 0, > 0, 0, 0,vr, vr, vr, vr, vk, vk, vk, vk")] VNCLIP) > @@ -3697,8 +3729,10 @@ > (match_operand 6 "const_int_operand" " i, > i, i, i, i, i") > (match_operand 7 "const_int_operand" " i, > i, i, i, i, i") > (match_operand 8 "const_int_operand" " i, > i, i, i, i, i") > + (match_operand 9 "const_int_operand" > " i, i, i, i, i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE) > (unspec:<V_DOUBLE_TRUNC> > [(match_operand:VWEXTI 3 "register_operand" " 0, > 0, 0, 0, vr, vr") > (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, > rK, rK, rK, rK, rK")] VNCLIP) > -- > 2.36.1 >
