Yeah. I know.
Like ARM does everywhere:
(define_expand "vcond<SVE_ALL:mode><SVE_I:mode>"
[(set (match_operand:SVE_ALL 0 "register_operand")
(if_then_else:SVE_ALL
(match_operator 3 "comparison_operator"
[(match_operand:SVE_I 4 "register_operand")
(match_operand:SVE_I 5 "nonmemory_operand")])
(match_operand:SVE_ALL 1 "nonmemory_operand")
(match_operand:SVE_ALL 2 "nonmemory_operand")))]
"TARGET_SVE && <SVE_ALL:container_bits> == <SVE_I:container_bits>"
{
aarch64_expand_sve_vcond (<SVE_ALL:MODE>mode, <SVE_I:MODE>mode, operands);
DONE;
}
)
passing "operands" looks codes much cleaner.
Hi, kito. Could you take a look at the V2 refactor patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/619291.html
This is important for us since we can't post more autovec patches without
refactor patch.
Thanks
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-23 16:45
To: juzhe.zh...@rivai.ai
CC: Robin Dapp; gcc-patches; Kito.cheng; palmer; palmer; jeffreyalaw
Subject: Re: Re: [PATCH] RISC-V: Refactor the framework of RVV
auto-vectorization
> ARM uses rtx operands[] in many places and I personally prefer this way since
> it will make codes much cleaner.
> I dislike the way making the function argument with multiple operand ,like
> this:
> void func(rtx dest, rtx src1, rtx src2, ....)
> If we are doing this, we will need to add helpers forever...
Don't forget we are using C++, so we have function overloading or
default arguments :)
