It's long mail but I think this should explain most high level concept why I did this:
I guess I skipped too much story about the VLS-mode support; VLS-mode support can be split into the middle-end and back-end. # Middle-end As Richard mentioned, those VLS types can be held by VLA-modes; for example, int32x4_t can be held by VNx4SI mode, so IMO there are three different options here: 1) use VLS type with VLS mode in middle-end, 2) use VLS type with VLA mode in middle-end 3) use VLA type with VLA mode. Option 2 might be weird and not natural to implement in GCC, so let me ignore that. Option 3 is a possible way, and actually, I did that on our downstream compiler, and then...we found a fact that is not friendly to optimization; give a few practical examples here VLA type is hard to present a vector constructor other than a step or splat/duplicated value, we need to push those value into memory first - and then load by len_load, okay, so constant propagation and folding can't work well here - since it's hard to evaluate that with unknown vector length. And it is also not friendly to pointer alias - because the length is unknown, so GCC must be conservative on this, which will block some optimization due to AA issues. So IMO the use the VLS-type with VLS mode is the best way in the middle-end. # Back-end OK, it's back-end time; we have two options in the back-end to support the VLS-type: support that with VLS mode or VLA mode. What's the meaning of support with VLA mode? convert VLS-type stuff into VLA mode pattern and give the right length information - then everything works. But what is wrong with this path? Again, similar issues in the back-end: the propagation and folding with constant vector will be limited when we hold in VLA type - we can't be held const_vector other than splat/duplicated value or step value; it can't even be held during the combine process, give an example here, we have a = {1, 2, 3, 4} and b = {4, 3, 2, 1}, this can be easily present at VLS mode RTL, but impossible to present in VLA mode RLT, and then we can folding to a+b to {5, 5, 5, 5}, but VLA mode will get a bunch of problems to optimize those stuff. And also the stack issue mentioned before - unless we can teach RA to track the length used for each register with VLA mode, I believe it would be terrible for RA... # Back to this patch Ju-Zhe has suggested we could reuse VLA pattern for VLS mode, I considered that before, however, I feel that might not be friendly with combine pass, because our VLA pattern is kind of complicated than the plain VLS pattern, BUT I believe we will improve that in the near future :P so I think that it should be reasonable just to use the same pattern - then we could just add VLS mode to the mode iterator to support that without magic mode changing, I can understand that really seems very unsafe.