On Thu, 01 Jun 2023 09:48:47 PDT (-0700), jeffreya...@gmail.com wrote:
On 6/1/23 01:01, juzhe.zh...@rivai.ai wrote:
I plan to implement BF16 vector in GCC but still waiting for ISA
ratified since GCC policy doesn't allow un-ratified ISA.
Right. So those specs need to move along further before we can start
integrating code.
Currently, we are working on INT8,INT16,INT32,INT64,FP16,FP32,FP64
auto-vectorizaiton.
It should very simple BF16 in current vector framework in GCC.
In prior architectures I've worked on the bulk of BF16 work was just
adding additional entries to existing iterators. So I agree, it should
be very simple :-)
We should also have someone who's a bit more plugged in to floating
point check to make sure the RISC-V bfloat16 semantics match IEEE. I
don't see any issues, but I'm not really a FP person so I'm not sure.
There were certainly a lot of subtlies for the other FP bits, so even if
the implementation just plumbs straight through IMO it's worth checking.
We have one FP person at Rivos, I can try and rope him in if you want?
Happy to have someone else do it, though, as he's usually pretty busy ;)
