lgtm, thanks for fixing this :)
On Wed, Jun 7, 2023 at 10:19 AM Pan Li via Gcc-patches <gcc-patches@gcc.gnu.org> wrote: > > From: Pan Li <pan2...@intel.com> > > This patch would like to fix the incorrect requirement of the vector > builtin types for the ZVFH/ZVFHMIN extension. The incorrect requirement > will result in the ops mismatch with iterators, and then ICE will be > triggered if ZVFH/ZVFHMIN is not given. > > Sorry for inconviensient. > > Signed-off-by: Pan Li <pan2...@intel.com> > > gcc/ChangeLog: > > * config/riscv/riscv-vector-builtins-types.def > (vfloat32mf2_t): Take RVV_REQUIRE_ELEN_FP_16 as requirement. > (vfloat32m1_t): Ditto. > (vfloat32m2_t): Ditto. > (vfloat32m4_t): Ditto. > (vfloat32m8_t): Ditto. > (vint16mf4_t): Ditto. > (vint16mf2_t): Ditto. > (vint16m1_t): Ditto. > (vint16m2_t): Ditto. > (vint16m4_t): Ditto. > (vint16m8_t): Ditto. > (vuint16mf4_t): Ditto. > (vuint16mf2_t): Ditto. > (vuint16m1_t): Ditto. > (vuint16m2_t): Ditto. > (vuint16m4_t): Ditto. > (vuint16m8_t): Ditto. > (vint32mf2_t): Ditto. > (vint32m1_t): Ditto. > (vint32m2_t): Ditto. > (vint32m4_t): Ditto. > (vint32m8_t): Ditto. > (vuint32mf2_t): Ditto. > (vuint32m1_t): Ditto. > (vuint32m2_t): Ditto. > (vuint32m4_t): Ditto. > (vuint32m8_t): Ditto. > --- > .../riscv/riscv-vector-builtins-types.def | 66 +++++++++---------- > 1 file changed, 33 insertions(+), 33 deletions(-) > > diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def > b/gcc/config/riscv/riscv-vector-builtins-types.def > index bd3deae8340..589ea532727 100644 > --- a/gcc/config/riscv/riscv-vector-builtins-types.def > +++ b/gcc/config/riscv/riscv-vector-builtins-types.def > @@ -518,23 +518,23 @@ DEF_RVV_FULL_V_U_OPS (vuint64m2_t, RVV_REQUIRE_FULL_V) > DEF_RVV_FULL_V_U_OPS (vuint64m4_t, RVV_REQUIRE_FULL_V) > DEF_RVV_FULL_V_U_OPS (vuint64m8_t, RVV_REQUIRE_FULL_V) > > -DEF_RVV_WEXTF_OPS (vfloat32mf2_t, TARGET_ZVFH | RVV_REQUIRE_ELEN_FP_32 | > RVV_REQUIRE_MIN_VLEN_64) > -DEF_RVV_WEXTF_OPS (vfloat32m1_t, TARGET_ZVFH | RVV_REQUIRE_ELEN_FP_32) > -DEF_RVV_WEXTF_OPS (vfloat32m2_t, TARGET_ZVFH | RVV_REQUIRE_ELEN_FP_32) > -DEF_RVV_WEXTF_OPS (vfloat32m4_t, TARGET_ZVFH | RVV_REQUIRE_ELEN_FP_32) > -DEF_RVV_WEXTF_OPS (vfloat32m8_t, TARGET_ZVFH | RVV_REQUIRE_ELEN_FP_32) > +DEF_RVV_WEXTF_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_16 | > RVV_REQUIRE_MIN_VLEN_64) > +DEF_RVV_WEXTF_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_16) > +DEF_RVV_WEXTF_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_16) > +DEF_RVV_WEXTF_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_16) > +DEF_RVV_WEXTF_OPS (vfloat32m8_t, RVV_REQUIRE_ELEN_FP_16) > > DEF_RVV_WEXTF_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64) > DEF_RVV_WEXTF_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64) > DEF_RVV_WEXTF_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64) > DEF_RVV_WEXTF_OPS (vfloat64m8_t, RVV_REQUIRE_ELEN_FP_64) > > -DEF_RVV_CONVERT_I_OPS (vint16mf4_t, TARGET_ZVFH | RVV_REQUIRE_MIN_VLEN_64) > -DEF_RVV_CONVERT_I_OPS (vint16mf2_t, TARGET_ZVFH) > -DEF_RVV_CONVERT_I_OPS (vint16m1_t, TARGET_ZVFH) > -DEF_RVV_CONVERT_I_OPS (vint16m2_t, TARGET_ZVFH) > -DEF_RVV_CONVERT_I_OPS (vint16m4_t, TARGET_ZVFH) > -DEF_RVV_CONVERT_I_OPS (vint16m8_t, TARGET_ZVFH) > +DEF_RVV_CONVERT_I_OPS (vint16mf4_t, RVV_REQUIRE_ELEN_FP_16 | > RVV_REQUIRE_MIN_VLEN_64) > +DEF_RVV_CONVERT_I_OPS (vint16mf2_t, RVV_REQUIRE_ELEN_FP_16) > +DEF_RVV_CONVERT_I_OPS (vint16m1_t, RVV_REQUIRE_ELEN_FP_16) > +DEF_RVV_CONVERT_I_OPS (vint16m2_t, RVV_REQUIRE_ELEN_FP_16) > +DEF_RVV_CONVERT_I_OPS (vint16m4_t, RVV_REQUIRE_ELEN_FP_16) > +DEF_RVV_CONVERT_I_OPS (vint16m8_t, RVV_REQUIRE_ELEN_FP_16) > > DEF_RVV_CONVERT_I_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64) > DEF_RVV_CONVERT_I_OPS (vint32m1_t, 0) > @@ -546,12 +546,12 @@ DEF_RVV_CONVERT_I_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64) > DEF_RVV_CONVERT_I_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64) > DEF_RVV_CONVERT_I_OPS (vint64m8_t, RVV_REQUIRE_ELEN_64) > > -DEF_RVV_CONVERT_U_OPS (vuint16mf4_t, TARGET_ZVFH | RVV_REQUIRE_MIN_VLEN_64) > -DEF_RVV_CONVERT_U_OPS (vuint16mf2_t, TARGET_ZVFH) > -DEF_RVV_CONVERT_U_OPS (vuint16m1_t, TARGET_ZVFH) > -DEF_RVV_CONVERT_U_OPS (vuint16m2_t, TARGET_ZVFH) > -DEF_RVV_CONVERT_U_OPS (vuint16m4_t, TARGET_ZVFH) > -DEF_RVV_CONVERT_U_OPS (vuint16m8_t, TARGET_ZVFH) > +DEF_RVV_CONVERT_U_OPS (vuint16mf4_t, RVV_REQUIRE_ELEN_FP_16 | > RVV_REQUIRE_MIN_VLEN_64) > +DEF_RVV_CONVERT_U_OPS (vuint16mf2_t, RVV_REQUIRE_ELEN_FP_16) > +DEF_RVV_CONVERT_U_OPS (vuint16m1_t, RVV_REQUIRE_ELEN_FP_16) > +DEF_RVV_CONVERT_U_OPS (vuint16m2_t, RVV_REQUIRE_ELEN_FP_16) > +DEF_RVV_CONVERT_U_OPS (vuint16m4_t, RVV_REQUIRE_ELEN_FP_16) > +DEF_RVV_CONVERT_U_OPS (vuint16m8_t, RVV_REQUIRE_ELEN_FP_16) > > DEF_RVV_CONVERT_U_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64) > DEF_RVV_CONVERT_U_OPS (vuint32m1_t, 0) > @@ -563,22 +563,22 @@ DEF_RVV_CONVERT_U_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64) > DEF_RVV_CONVERT_U_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64) > DEF_RVV_CONVERT_U_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64) > > -DEF_RVV_WCONVERT_I_OPS (vint32mf2_t, TARGET_ZVFH | RVV_REQUIRE_MIN_VLEN_64) > -DEF_RVV_WCONVERT_I_OPS (vint32m1_t, TARGET_ZVFH) > -DEF_RVV_WCONVERT_I_OPS (vint32m2_t, TARGET_ZVFH) > -DEF_RVV_WCONVERT_I_OPS (vint32m4_t, TARGET_ZVFH) > -DEF_RVV_WCONVERT_I_OPS (vint32m8_t, TARGET_ZVFH) > +DEF_RVV_WCONVERT_I_OPS (vint32mf2_t, RVV_REQUIRE_ELEN_FP_16 | > RVV_REQUIRE_MIN_VLEN_64) > +DEF_RVV_WCONVERT_I_OPS (vint32m1_t, RVV_REQUIRE_ELEN_FP_16) > +DEF_RVV_WCONVERT_I_OPS (vint32m2_t, RVV_REQUIRE_ELEN_FP_16) > +DEF_RVV_WCONVERT_I_OPS (vint32m4_t, RVV_REQUIRE_ELEN_FP_16) > +DEF_RVV_WCONVERT_I_OPS (vint32m8_t, RVV_REQUIRE_ELEN_FP_16) > > DEF_RVV_WCONVERT_I_OPS (vint64m1_t, RVV_REQUIRE_ELEN_FP_32 | > RVV_REQUIRE_ELEN_64) > DEF_RVV_WCONVERT_I_OPS (vint64m2_t, RVV_REQUIRE_ELEN_FP_32 | > RVV_REQUIRE_ELEN_64) > DEF_RVV_WCONVERT_I_OPS (vint64m4_t, RVV_REQUIRE_ELEN_FP_32 | > RVV_REQUIRE_ELEN_64) > DEF_RVV_WCONVERT_I_OPS (vint64m8_t, RVV_REQUIRE_ELEN_FP_32 | > RVV_REQUIRE_ELEN_64) > > -DEF_RVV_WCONVERT_U_OPS (vuint32mf2_t, TARGET_ZVFH | RVV_REQUIRE_MIN_VLEN_64) > -DEF_RVV_WCONVERT_U_OPS (vuint32m1_t, TARGET_ZVFH) > -DEF_RVV_WCONVERT_U_OPS (vuint32m2_t, TARGET_ZVFH) > -DEF_RVV_WCONVERT_U_OPS (vuint32m4_t, TARGET_ZVFH) > -DEF_RVV_WCONVERT_U_OPS (vuint32m8_t, TARGET_ZVFH) > +DEF_RVV_WCONVERT_U_OPS (vuint32mf2_t, RVV_REQUIRE_ELEN_FP_16 | > RVV_REQUIRE_MIN_VLEN_64) > +DEF_RVV_WCONVERT_U_OPS (vuint32m1_t, RVV_REQUIRE_ELEN_FP_16) > +DEF_RVV_WCONVERT_U_OPS (vuint32m2_t, RVV_REQUIRE_ELEN_FP_16) > +DEF_RVV_WCONVERT_U_OPS (vuint32m4_t, RVV_REQUIRE_ELEN_FP_16) > +DEF_RVV_WCONVERT_U_OPS (vuint32m8_t, RVV_REQUIRE_ELEN_FP_16) > > DEF_RVV_WCONVERT_U_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_FP_32 | > RVV_REQUIRE_ELEN_64) > DEF_RVV_WCONVERT_U_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_FP_32 | > RVV_REQUIRE_ELEN_64) > @@ -634,12 +634,12 @@ DEF_RVV_WU_OPS (vuint32m2_t, 0) > DEF_RVV_WU_OPS (vuint32m4_t, 0) > DEF_RVV_WU_OPS (vuint32m8_t, 0) > > -DEF_RVV_WF_OPS (vfloat16mf4_t, TARGET_ZVFH | RVV_REQUIRE_MIN_VLEN_64) > -DEF_RVV_WF_OPS (vfloat16mf2_t, TARGET_ZVFH) > -DEF_RVV_WF_OPS (vfloat16m1_t, TARGET_ZVFH) > -DEF_RVV_WF_OPS (vfloat16m2_t, TARGET_ZVFH) > -DEF_RVV_WF_OPS (vfloat16m4_t, TARGET_ZVFH) > -DEF_RVV_WF_OPS (vfloat16m8_t, TARGET_ZVFH) > +DEF_RVV_WF_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | > RVV_REQUIRE_MIN_VLEN_64) > +DEF_RVV_WF_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16) > +DEF_RVV_WF_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16) > +DEF_RVV_WF_OPS (vfloat16m2_t, RVV_REQUIRE_ELEN_FP_16) > +DEF_RVV_WF_OPS (vfloat16m4_t, RVV_REQUIRE_ELEN_FP_16) > +DEF_RVV_WF_OPS (vfloat16m8_t, RVV_REQUIRE_ELEN_FP_16) > > DEF_RVV_WF_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | > RVV_REQUIRE_MIN_VLEN_64) > DEF_RVV_WF_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32) > -- > 2.34.1 >
