Minor change in PATCH V5, please help to turn to V5 as below, sorry for inconvenient.
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620890.html Pan From: Li, Pan2 Sent: Wednesday, June 7, 2023 2:57 PM To: 'juzhe.zh...@rivai.ai' <juzhe.zh...@rivai.ai>; 'gcc-patches' <gcc-patches@gcc.gnu.org> Cc: 'Kito.cheng' <kito.ch...@sifive.com>; Wang, Yanzhang <yanzhang.w...@intel.com> Subject: RE: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. Update the PATCH V4 as below, sorry for missed the v4 prefix in subject. https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620879.html Pan From: Li, Pan2 Sent: Wednesday, June 7, 2023 2:21 PM To: juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>; gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>> Cc: Kito.cheng <kito.ch...@sifive.com<mailto:kito.ch...@sifive.com>>; Wang, Yanzhang <yanzhang.w...@intel.com<mailto:yanzhang.w...@intel.com>> Subject: RE: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. Thanks JuZhe, make sense, will update the V4 for this change. Pan From: juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai> <juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>> Sent: Wednesday, June 7, 2023 12:21 PM To: Li, Pan2 <pan2...@intel.com<mailto:pan2...@intel.com>>; gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>> Cc: Kito.cheng <kito.ch...@sifive.com<mailto:kito.ch...@sifive.com>>; Li, Pan2 <pan2...@intel.com<mailto:pan2...@intel.com>>; Wang, Yanzhang <yanzhang.w...@intel.com<mailto:yanzhang.w...@intel.com>> Subject: Re: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. HI, + (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") + (VNx2SF "TARGET_VECTOR_ELEN_FP_16") + (VNx4SF "TARGET_VECTOR_ELEN_FP_16") + (VNx8SF "TARGET_VECTOR_ELEN_FP_16") + (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") + (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128") Add TARGET_VECTOR_ELEN_FP_32 here, for FP16->FP32 conversion, we need both ELEN_FP16 and ELEN_FP32 enable. ________________________________ juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai> From: pan2.li<mailto:pan2...@intel.com> Date: 2023-06-07 11:00 To: gcc-patches<mailto:gcc-patches@gcc.gnu.org> CC: juzhe.zhong<mailto:juzhe.zh...@rivai.ai>; kito.cheng<mailto:kito.ch...@sifive.com>; pan2.li<mailto:pan2...@intel.com>; yanzhang.wang<mailto:yanzhang.w...@intel.com> Subject: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. From: Pan Li <pan2...@intel.com<mailto:pan2...@intel.com>> This patch would like to refactor the requirement of both the ZVFH and ZVFHMIN. The related define_insn and iterator will take the requirement based on the ZVFHMIN and ZVFH. Please note the ZVFH will cover the ZVFHMIN instructions. This patch add one test for this. Signed-off-by: Pan Li <pan2...@intel.com<mailto:pan2...@intel.com>> gcc/ChangeLog: * config/riscv/vector-iterators.md: Add requirement to VF, VWEXTF and VWCONVERTI, add V_CONVERT_F and VCONVERTF. * config/riscv/vector.md: Adjust FP convert to V_CONVERT_F and VCONVERTF. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test. --- gcc/config/riscv/vector-iterators.md | 68 +++++++++++++------ gcc/config/riscv/vector.md | 46 ++++++------- .../riscv/rvv/base/zvfh-over-zvfhmin.c | 25 +++++++ 3 files changed, 97 insertions(+), 42 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index f4946d84449..1dc82bd44d3 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -296,13 +296,13 @@ (define_mode_iterator VWI_ZVE32 [ ]) (define_mode_iterator VF [ - (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") - (VNx2HF "TARGET_VECTOR_ELEN_FP_16") - (VNx4HF "TARGET_VECTOR_ELEN_FP_16") - (VNx8HF "TARGET_VECTOR_ELEN_FP_16") - (VNx16HF "TARGET_VECTOR_ELEN_FP_16") - (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") - (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128") + (VNx1HF "TARGET_ZVFH && TARGET_MIN_VLEN < 128") + (VNx2HF "TARGET_ZVFH") + (VNx4HF "TARGET_ZVFH") + (VNx8HF "TARGET_ZVFH") + (VNx16HF "TARGET_ZVFH") + (VNx32HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32") + (VNx64HF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128") (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") (VNx2SF "TARGET_VECTOR_ELEN_FP_32") @@ -497,12 +497,12 @@ (define_mode_iterator VWEXTI [ ]) (define_mode_iterator VWEXTF [ - (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") - (VNx2SF "TARGET_VECTOR_ELEN_FP_32") - (VNx4SF "TARGET_VECTOR_ELEN_FP_32") - (VNx8SF "TARGET_VECTOR_ELEN_FP_32") - (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") - (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") + (VNx1SF "TARGET_ZVFH && TARGET_MIN_VLEN < 128") + (VNx2SF "TARGET_ZVFH") + (VNx4SF "TARGET_ZVFH") + (VNx8SF "TARGET_ZVFH") + (VNx16SF "TARGET_ZVFH && TARGET_MIN_VLEN > 32") + (VNx32SF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128") (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128") (VNx2DF "TARGET_VECTOR_ELEN_FP_64") @@ -512,12 +512,12 @@ (define_mode_iterator VWEXTF [ ]) (define_mode_iterator VWCONVERTI [ - (VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16") - (VNx2SI "TARGET_VECTOR_ELEN_FP_16") - (VNx4SI "TARGET_VECTOR_ELEN_FP_16") - (VNx8SI "TARGET_VECTOR_ELEN_FP_16") - (VNx16SI "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16") - (VNx32SI "TARGET_MIN_VLEN >= 128 && TARGET_VECTOR_ELEN_FP_16") + (VNx1SI "TARGET_ZVFH && TARGET_MIN_VLEN < 128") + (VNx2SI "TARGET_ZVFH") + (VNx4SI "TARGET_ZVFH") + (VNx8SI "TARGET_ZVFH") + (VNx16SI "TARGET_ZVFH && TARGET_MIN_VLEN > 32") + (VNx32SI "TARGET_ZVFH && TARGET_MIN_VLEN >= 128") (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32") @@ -526,6 +526,21 @@ (define_mode_iterator VWCONVERTI [ (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") ]) +(define_mode_iterator VCONVERTF [ + (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") + (VNx2SF "TARGET_VECTOR_ELEN_FP_16") + (VNx4SF "TARGET_VECTOR_ELEN_FP_16") + (VNx8SF "TARGET_VECTOR_ELEN_FP_16") + (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") + (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128") + + (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128") + (VNx2DF "TARGET_VECTOR_ELEN_FP_64") + (VNx4DF "TARGET_VECTOR_ELEN_FP_64") + (VNx8DF "TARGET_VECTOR_ELEN_FP_64") + (VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128") +]) + (define_mode_iterator VQEXTI [ (VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >= 128") (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64") @@ -1181,6 +1196,21 @@ (define_mode_attr V_DOUBLE_TRUNC [ (VNx16DF "VNx16SF") ]) +(define_mode_attr V_CONVERT_F [ + (VNx1SF "VNx1HF") + (VNx2SF "VNx2HF") + (VNx4SF "VNx4HF") + (VNx8SF "VNx8HF") + (VNx16SF "VNx16HF") + (VNx32SF "VNx32HF") + + (VNx1DF "VNx1SF") + (VNx2DF "VNx2SF") + (VNx4DF "VNx4SF") + (VNx8DF "VNx8SF") + (VNx16DF "VNx16SF") +]) + (define_mode_attr V_QUAD_TRUNC [ (VNx1SI "VNx1QI") (VNx2SI "VNx2QI") (VNx4SI "VNx4QI") (VNx8SI "VNx8QI") (VNx16SI "VNx16QI") (VNx32SI "VNx32QI") diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 1d1847bd85a..97162b07642 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7106,23 +7106,23 @@ (define_insn "@pred_widen_<float_cvt><mode>" (set_attr "mode" "<VNCONVERT>")]) (define_insn "@pred_extend<mode>" - [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr") - (if_then_else:VWEXTF + [(set (match_operand:VCONVERTF 0 "register_operand" "=&vr, &vr") + (if_then_else:VCONVERTF (unspec:<VM> - [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rK, rK") - (match_operand 5 "const_int_operand" " i, i") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK") + (match_operand 5 "const_int_operand" " i, i") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (float_extend:VWEXTF - (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr")) - (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))] + (float_extend:VCONVERTF + (match_operand:<V_CONVERT_F> 3 "register_operand" " vr, vr")) + (match_operand:VCONVERTF 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vfwcvt.f.f.v\t%0,%3%p1" [(set_attr "type" "vfwcvtftof") - (set_attr "mode" "<V_DOUBLE_TRUNC>")]) + (set_attr "mode" "<V_CONVERT_F>")]) ;; ------------------------------------------------------------------------------- ;; ---- Predicated floating-point narrow conversions @@ -7193,25 +7193,25 @@ (define_insn "@pred_narrow_<float_cvt><mode>" (set_attr "mode" "<VNCONVERT>")]) (define_insn "@pred_trunc<mode>" - [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr") - (if_then_else:<V_DOUBLE_TRUNC> + [(set (match_operand:<V_CONVERT_F> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr") + (if_then_else:<V_CONVERT_F> (unspec:<VM> - [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK") - (match_operand 5 "const_int_operand" " i, i, i, i, i, i") - (match_operand 6 "const_int_operand" " i, i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i, i") + [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK") + (match_operand 5 "const_int_operand" " i, i, i, i, i, i") + (match_operand 6 "const_int_operand" " i, i, i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) - (float_truncate:<V_DOUBLE_TRUNC> - (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr")) - (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))] + (float_truncate:<V_CONVERT_F> + (match_operand:VCONVERTF 3 "register_operand" " 0, 0, 0, 0, vr, vr")) + (match_operand:<V_CONVERT_F> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))] "TARGET_VECTOR" "vfncvt.f.f.w\t%0,%3%p1" [(set_attr "type" "vfncvtftof") - (set_attr "mode" "<V_DOUBLE_TRUNC>")]) + (set_attr "mode" "<V_CONVERT_F>")]) (define_insn "@pred_rod_trunc<mode>" [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c new file mode 100644 index 00000000000..32d6657775c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */ + +#include "riscv_vector.h" + +vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) { + return __riscv_vfncvt_f_f_w_f16mf4(src, vl); +} + +vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) { + return __riscv_vfncvt_f_f_w_f16m4(src, vl); +} + +vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) { + return __riscv_vfwcvt_f_f_v_f32mf2(src, vl); +} + +vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) { + return __riscv_vfwcvt_f_f_v_f32m8(src, vl); +} + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */ +/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */ -- 2.34.1
