Hmmm, I still saw some fail on testsuite after applying this patch, most are because the testcase has used vector type as argument or return value, but .. vector-abi-1.c should not fail I think?
For other fails, I would suggest you could just add -Wno-psabi to rvv.exp === gcc: Unexpected fails for rv64imafdcv lp64d medlow === FAIL: gcc.target/riscv/vector-abi-1.c -O0 (test for warnings, line 7) FAIL: gcc.target/riscv/vector-abi-1.c -O1 (test for warnings, line 7) FAIL: gcc.target/riscv/vector-abi-1.c -O2 (test for warnings, line 7) FAIL: gcc.target/riscv/vector-abi-1.c -O2 -flto -fno-use-linker-plugin -flto-partition=none (test for warnings, line 7) FAIL: gcc.target/riscv/vector-abi-1.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects (test for warnings, line 7) FAIL: gcc.target/riscv/vector-abi-1.c -O3 -g (test for warnings, line 7) FAIL: gcc.target/riscv/vector-abi-1.c -Os (test for warnings, line 7) FAIL: gcc.target/riscv/vector-abi-1.c -Og -g (test for warnings, line 7) FAIL: gcc.target/riscv/vector-abi-1.c -Oz (test for warnings, line 7) FAIL: gcc.target/riscv/rvv/base/binop_vx_constraint-120.c (test for excess errors) FAIL: gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c (test for excess errors) FAIL: gcc.target/riscv/rvv/base/mask_insn_shortcut.c (test for excess errors) FAIL: gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c (test for excess errors) FAIL: gcc.target/riscv/rvv/base/pr110109-2.c (test for excess errors) FAIL: gcc.target/riscv/rvv/base/scalar_move-9.c (test for excess errors) FAIL: gcc.target/riscv/rvv/base/vlmul_ext-1.c (test for excess errors) FAIL: gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c (test for excess errors) FAIL: gcc.target/riscv/rvv/base/zvfh-intrinsic.c (test for excess errors) FAIL: gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c (test for excess errors) FAIL: gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c (test for excess errors) ========= Summary of gcc testsuite ========= | # of unexpected case / # of unique unexpected case | gcc | g++ | gfortran | rv32imafdc/ ilp32d/ medlow | 20 / 12 | 0 / 0 | 0 / 0 | rv32imafdcv/ ilp32d/ medlow | 25 / 14 | 22 / 22 | 0 / 0 | rv64imafdc/ lp64d/ medlow | 20 / 12 | 0 / 0 | 0 / 0 | rv64imafdcv/ lp64d/ medlow | 20 / 12 | 21 / 21 | 0 / 0 | On Fri, Jun 9, 2023 at 2:02 PM yanzhang.wang--- via Gcc-patches <gcc-patches@gcc.gnu.org> wrote: > > From: Yanzhang Wang <yanzhang.w...@intel.com> > > This patch adds support to check function's argument or return is vector type > and throw warning if yes. > > There're two exceptions, > - The vector_size attribute. > - The intrinsic functions. > > gcc/ChangeLog: > > * config/riscv/riscv-protos.h (riscv_init_cumulative_args): Set > warning flag if func is not builtin > * config/riscv/riscv.cc > (riscv_scalable_vector_type_p): Determine whether the type is > scalable vector. > (riscv_arg_has_vector): Determine whether the arg is vector type. > (riscv_pass_in_vector_p): Check the vector type param is passed by > value. > (riscv_init_cumulative_args): The same as header. > (riscv_get_arg_info): Add the checking. > (riscv_function_value): Check the func return and set warning flag > * config/riscv/riscv.h (INIT_CUMULATIVE_ARGS): Add a flag to > determine whether warning psabi or not. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/vector-abi-1.c: New test. > * gcc.target/riscv/vector-abi-2.c: New test. > * gcc.target/riscv/vector-abi-3.c: New test. > * gcc.target/riscv/vector-abi-4.c: New test. > * gcc.target/riscv/vector-abi-5.c: New test. > * gcc.target/riscv/vector-abi-6.c: New test. > > Signed-off-by: Yanzhang Wang <yanzhang.w...@intel.com> > Co-authored-by: Kito Cheng <kito.ch...@sifive.com> > --- > gcc/config/riscv/riscv-protos.h | 2 + > gcc/config/riscv/riscv.cc | 112 +++++++++++++++++- > gcc/config/riscv/riscv.h | 5 +- > gcc/testsuite/gcc.target/riscv/vector-abi-1.c | 14 +++ > gcc/testsuite/gcc.target/riscv/vector-abi-2.c | 15 +++ > gcc/testsuite/gcc.target/riscv/vector-abi-3.c | 14 +++ > gcc/testsuite/gcc.target/riscv/vector-abi-4.c | 16 +++ > gcc/testsuite/gcc.target/riscv/vector-abi-5.c | 15 +++ > gcc/testsuite/gcc.target/riscv/vector-abi-6.c | 20 ++++ > 9 files changed, 211 insertions(+), 2 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-1.c > create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-2.c > create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-3.c > create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-4.c > create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-5.c > create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-6.c > > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h > index e41f65a0894..d8f42778565 100644 > --- a/gcc/config/riscv/riscv-protos.h > +++ b/gcc/config/riscv/riscv-protos.h > @@ -235,4 +235,6 @@ extern const char* > th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE); > #endif > > +void riscv_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, int); > + > #endif /* ! GCC_RISCV_PROTOS_H */ > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 76eee4a55e9..3286656ecba 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -3728,6 +3728,99 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned > regno1, > GEN_INT (offset2)))); > } > > +/* Use the TYPE_SIZE to distinguish the type with vector_size attribute and > + intrinsic vector type. Because we can't get the decl for the params. */ > + > +static bool > +riscv_scalable_vector_type_p (const_tree type) > +{ > + tree size = TYPE_SIZE (type); > + if (size && TREE_CODE (size) == INTEGER_CST) > + return false; > + > + /* For the data type like vint32m1_t, the size code is POLY_INT_CST. */ > + return true; > +} > + > +static bool > +riscv_arg_has_vector (const_tree type) > +{ > + bool is_vector = false; > + > + switch (TREE_CODE (type)) > + { > + case RECORD_TYPE: > + if (!COMPLETE_TYPE_P (type)) > + break; > + > + for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f)) > + if (TREE_CODE (f) == FIELD_DECL) > + { > + tree field_type = TREE_TYPE (f); > + if (!TYPE_P (field_type)) > + break; > + > + /* Ignore it if it's fixed length vector. */ > + if (VECTOR_TYPE_P (field_type)) > + is_vector = riscv_scalable_vector_type_p (field_type); > + else > + is_vector = riscv_arg_has_vector (field_type); > + } > + > + break; > + > + case VECTOR_TYPE: > + is_vector = riscv_scalable_vector_type_p (type); > + break; > + > + default: > + is_vector = false; > + break; > + } > + > + return is_vector; > +} > + > +/* Pass the type to check whether it's a vector type or contains vector type. > + Only check the value type and no checking for vector pointer type. */ > + > +static void > +riscv_pass_in_vector_p (const_tree type) > +{ > + static int warned = 0; > + > + if (type && riscv_arg_has_vector (type) && !warned) > + { > + warning (OPT_Wpsabi, "ABI for the scalable vector type is currently in > " > + "experimental stage and may changes in the upcoming version of > " > + "GCC."); > + warned = 1; > + } > +} > + > +/* Initialize a variable CUM of type CUMULATIVE_ARGS > + for a call to a function whose data type is FNTYPE. > + For a library call, FNTYPE is 0. */ > + > +void > +riscv_init_cumulative_args (CUMULATIVE_ARGS *cum, > + tree fntype, > + rtx libname, > + tree fndecl, > + int caller) > +{ > + memset (cum, 0, sizeof (*cum)); > + > + if (fndecl) > + { > + const tree_function_decl &fn > + = FUNCTION_DECL_CHECK (fndecl)->function_decl; > + > + if (fn.built_in_class == NOT_BUILT_IN) > + cum->rvv_psabi_warning = 1; > + } > +} > + > /* Fill INFO with information about a single argument, and return an > RTL pattern to pass or return the argument. CUM is the cumulative > state for earlier arguments. MODE is the mode of this argument and > @@ -3812,6 +3905,12 @@ riscv_get_arg_info (struct riscv_arg_info *info, const > CUMULATIVE_ARGS *cum, > } > } > > + if (cum->rvv_psabi_warning) > + { > + /* Only check existing of vector type. */ > + riscv_pass_in_vector_p (type); > + } > + > /* Work out the size of the argument. */ > num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE > (mode).to_constant (); > num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; > @@ -3899,7 +3998,18 @@ riscv_function_value (const_tree type, const_tree > func, machine_mode mode) > } > > memset (&args, 0, sizeof args); > - return riscv_get_arg_info (&info, &args, mode, type, true, true); > + > + const_tree arg_type = type; > + if (func && DECL_RESULT (func)) > + { > + const tree_function_decl &fn = FUNCTION_DECL_CHECK > (func)->function_decl; > + if (fn.built_in_class == NOT_BUILT_IN) > + args.rvv_psabi_warning = 1; > + > + arg_type = TREE_TYPE (DECL_RESULT (func)); > + } > + > + return riscv_get_arg_info (&info, &args, mode, arg_type, true, true); > } > > /* Implement TARGET_PASS_BY_REFERENCE. */ > diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h > index 66fb07d6652..cb10b63ef10 100644 > --- a/gcc/config/riscv/riscv.h > +++ b/gcc/config/riscv/riscv.h > @@ -671,6 +671,8 @@ typedef struct { > > /* Number of floating-point registers used so far, likewise. */ > unsigned int num_fprs; > + > + int rvv_psabi_warning; > } CUMULATIVE_ARGS; > > /* Initialize a variable CUM of type CUMULATIVE_ARGS > @@ -678,7 +680,8 @@ typedef struct { > For a library call, FNTYPE is 0. */ > > #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ > - memset (&(CUM), 0, sizeof (CUM)) > + riscv_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT), \ > + (N_NAMED_ARGS) != -1) > > #define EPILOGUE_USES(REGNO) riscv_epilogue_uses (REGNO) > > diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-1.c > b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c > new file mode 100644 > index 00000000000..969f14277a4 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c > @@ -0,0 +1,14 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */ > + > +#include "riscv_vector.h" > + > +void > +fun (vint32m1_t a) { } /* { dg-warning "the scalable vector type" } */ > + > +void > +bar () > +{ > + vint32m1_t a; > + fun (a); > +} > diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-2.c > b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c > new file mode 100644 > index 00000000000..63d97d30fc5 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c > @@ -0,0 +1,15 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ > +/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */ > + > +#include "riscv_vector.h" > + > +vint32m1_t > +fun (vint32m1_t* a) { return *a; } /* { dg-warning "the scalable vector > type" } */ > + > +void > +bar () > +{ > + vint32m1_t a; > + fun (&a); > +} > diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-3.c > b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c > new file mode 100644 > index 00000000000..90ece60cc6f > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c > @@ -0,0 +1,14 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ > + > +#include "riscv_vector.h" > + > +vint32m1_t* > +fun (vint32m1_t* a) { return a; } /* { dg-bogus "the scalable vector type" > } */ > + > +void > +bar () > +{ > + vint32m1_t a; > + fun (&a); > +} > diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-4.c > b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c > new file mode 100644 > index 00000000000..ecf6d4cc26b > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c > @@ -0,0 +1,16 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ > + > +#include "riscv_vector.h" > + > +typedef int v4si __attribute__ ((vector_size (16))); > + > +v4si > +fun (v4si a) { return a; } /* { dg-bogus "the scalable vector type" } */ > + > +void > +bar () > +{ > + v4si a; > + fun (a); > +} > diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-5.c > b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c > new file mode 100644 > index 00000000000..6053e0783b6 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c > @@ -0,0 +1,15 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ > + > +typedef int v4si __attribute__ ((vector_size (16))); > +struct A { int a; v4si b; }; > + > +void > +fun (struct A a) {} /* { dg-bogus "the scalable vector type" } */ > + > +void > +bar () > +{ > + struct A a; > + fun (a); > +} > diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-6.c > b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c > new file mode 100644 > index 00000000000..63bc4a89805 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c > @@ -0,0 +1,20 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ > +#include "riscv_vector.h" > + > +void > +foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, > + size_t n, int cond) { > + size_t vl; > + if (cond) > + vl = __riscv_vsetvlmax_e32m1(); > + else > + vl = __riscv_vsetvlmax_e16mf2(); > + for (size_t i = 0; i < n; i += 1) > + { > + vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl); /* { dg-bogus "the > scalable vector type" } */ > + vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl); > + vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl); > + __riscv_vse32_v_i32m1(out, c, vl); > + } > +} > -- > 2.40.1 >