LGTM
juzhe.zh...@rivai.ai <juzhe.zh...@rivai.ai> 於 2023年6月12日 週一 10:58 寫道：
> LGTM.
>
>
>
> juzhe.zh...@rivai.ai
>
> From: pan2.li
> Date: 2023-06-12 10:57
> To: gcc-patches
> CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang;
> kito.cheng
> Subject: [PATCH v1] RISC-V: Add test cases for RVV FP16 undefined and
> vlmul trunc
> From: Pan Li <pan2...@intel.com>
>
> This patch would like to add more tests for RVV FP16 undef and vlmul
> trunc, aka
>
> __riscv_vundefined_f16*();
> __riscv_vlmul_trunc_v_f16*_f16*();
>
> From the user's perspective, it is reasonable to do above operation
> when only ZVFHMIN is enabled. This patch would like to add new test
> cases to make sure the RVV FP16 vreinterpret works well as expected.
>
> Signed-off-by: Pan Li <pan2...@intel.com>
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Add test cases.
> * gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Ditto.
> ---
> .../riscv/rvv/base/zvfh-over-zvfhmin.c | 28 ++++++--
> .../riscv/rvv/base/zvfhmin-intrinsic.c | 66 +++++++++++++++----
> 2 files changed, 78 insertions(+), 16 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
> index ff9e0156a68..c3ed4191a36 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
> @@ -45,15 +45,33 @@ vfloat16m8_t
> test_vlmul_ext_v_f16mf4_f16m8(vfloat16mf4_t op1) {
> return __riscv_vlmul_ext_v_f16mf4_f16m8(op1);
> }
> +vfloat16mf4_t test_vlmul_trunc_v_f16mf2_f16mf4(vfloat16mf2_t op1) {
> + return __riscv_vlmul_trunc_v_f16mf2_f16mf4(op1);
> +}
> +
> +vfloat16m4_t test_vlmul_trunc_v_f16m8_f16m4(vfloat16m8_t op1) {
> + return __riscv_vlmul_trunc_v_f16m8_f16m4(op1);
> +}
> +
> +vfloat16mf4_t test_vundefined_f16mf4() {
> + return __riscv_vundefined_f16mf4();
> +}
> +
> +vfloat16m8_t test_vundefined_f16m8() {
> + return __riscv_vundefined_f16m8();
> +}
> +
> /* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 6 } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 8 } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
> /* { dg-final { scan-assembler-times
> {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
> /* { dg-final { scan-assembler-times
> {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
> -/* { dg-final { scan-assembler-times
> {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 6 } } */
> -/* { dg-final { scan-assembler-times
> {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */
> +/* { dg-final { scan-assembler-times
> {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 7 } } */
> +/* { dg-final { scan-assembler-times
> {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 6 } } */
> +/* { dg-final { scan-assembler-times
> {vl4re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */
> /* { dg-final { scan-assembler-times
> {vl8re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */
> -/* { dg-final { scan-assembler-times
> {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */
> +/* { dg-final { scan-assembler-times
> {vs4r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */
> +/* { dg-final { scan-assembler-times
> {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> index 68720e64926..8d39a2ed4c2 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> @@ -121,26 +121,70 @@ vfloat16m8_t
> test_vlmul_ext_v_f16mf4_f16m8(vfloat16mf4_t op1) {
> return __riscv_vlmul_ext_v_f16mf4_f16m8(op1);
> }
> +vfloat16mf4_t test_vlmul_trunc_v_f16mf2_f16mf4(vfloat16mf2_t op1) {
> + return __riscv_vlmul_trunc_v_f16mf2_f16mf4(op1);
> +}
> +
> +vfloat16mf4_t test_vlmul_trunc_v_f16m1_f16mf4(vfloat16m1_t op1) {
> + return __riscv_vlmul_trunc_v_f16m1_f16mf4(op1);
> +}
> +
> +vfloat16mf2_t test_vlmul_trunc_v_f16m1_f16mf2(vfloat16m1_t op1) {
> + return __riscv_vlmul_trunc_v_f16m1_f16mf2(op1);
> +}
> +
> +vfloat16mf4_t test_vlmul_trunc_v_f16m2_f16mf4(vfloat16m2_t op1) {
> + return __riscv_vlmul_trunc_v_f16m2_f16mf4(op1);
> +}
> +
> +vfloat16m1_t test_vlmul_trunc_v_f16m2_f16m1(vfloat16m2_t op1) {
> + return __riscv_vlmul_trunc_v_f16m2_f16m1(op1);
> +}
> +
> +vfloat16mf4_t test_vlmul_trunc_v_f16m4_f16mf4(vfloat16m4_t op1) {
> + return __riscv_vlmul_trunc_v_f16m4_f16mf4(op1);
> +}
> +
> +vfloat16m2_t test_vlmul_trunc_v_f16m4_f16m2(vfloat16m4_t op1) {
> + return __riscv_vlmul_trunc_v_f16m4_f16m2(op1);
> +}
> +
> +vfloat16mf4_t test_vlmul_trunc_v_f16m8_f16mf4(vfloat16m8_t op1) {
> + return __riscv_vlmul_trunc_v_f16m8_f16mf4(op1);
> +}
> +
> +vfloat16m4_t test_vlmul_trunc_v_f16m8_f16m4(vfloat16m8_t op1) {
> + return __riscv_vlmul_trunc_v_f16m8_f16m4(op1);
> +}
> +
> +vfloat16mf4_t test_vundefined_f16mf4() {
> + return __riscv_vundefined_f16mf4();
> +}
> +
> +vfloat16m8_t test_vundefined_f16m8() {
> + return __riscv_vundefined_f16m8();
> +}
> +
> /* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 12 } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 18 } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 6 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m2,\s*t[au],\s*m[au]} 1 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m4,\s*t[au],\s*m[au]} 1 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m8,\s*t[au],\s*m[au]} 5 } } */
> /* { dg-final { scan-assembler-times
> {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */
> /* { dg-final { scan-assembler-times
> {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
> -/* { dg-final { scan-assembler-times
> {vle16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 14 } } */
> -/* { dg-final { scan-assembler-times
> {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 8 } } */
> -/* { dg-final { scan-assembler-times
> {vl1re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 2 } } */
> -/* { dg-final { scan-assembler-times
> {vl2re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 2 } } */
> +/* { dg-final { scan-assembler-times
> {vle16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 20 } } */
> +/* { dg-final { scan-assembler-times
> {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 15 } } */
> +/* { dg-final { scan-assembler-times
> {vl1re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
> +/* { dg-final { scan-assembler-times
> {vl2re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
> /* { dg-final { scan-assembler-times
> {vl8re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */
> -/* { dg-final { scan-assembler-times
> {vl4re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 2 } } */
> -/* { dg-final { scan-assembler-times
> {vs1r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
> -/* { dg-final { scan-assembler-times
> {vs2r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
> -/* { dg-final { scan-assembler-times
> {vs4r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
> -/* { dg-final { scan-assembler-times
> {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 11 } } */
> +/* { dg-final { scan-assembler-times
> {vl4re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
> +/* { dg-final { scan-assembler-times
> {vs1r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */
> +/* { dg-final { scan-assembler-times
> {vs2r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */
> +/* { dg-final { scan-assembler-times
> {vs4r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */
> +/* { dg-final { scan-assembler-times
> {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> --
> 2.34.1
>
>
>
