Hi Richard, For the following reduced test-case taken from PR: #include "arm_sve.h" svuint32_t l() { alignas(16) const unsigned int lanes[4] = {0, 0, 0, 0}; return svld1rq_u32(svptrue_b8(), lanes); }
compiling with -O3 -mcpu=generic+sve results in following ICE: during GIMPLE pass: fre pr110280.c: In function 'l': pr110280.c:5:1: internal compiler error: in eliminate_stmt, at tree-ssa-sccvn.cc:6890 5 | } | ^ 0x865fb1 eliminate_dom_walker::eliminate_stmt(basic_block_def*, gimple_stmt_iterator*) ../../gcc/gcc/tree-ssa-sccvn.cc:6890 0x120bf4d eliminate_dom_walker::before_dom_children(basic_block_def*) ../../gcc/gcc/tree-ssa-sccvn.cc:7324 0x120bf4d eliminate_dom_walker::before_dom_children(basic_block_def*) ../../gcc/gcc/tree-ssa-sccvn.cc:7257 0x1aeec77 dom_walker::walk(basic_block_def*) ../../gcc/gcc/domwalk.cc:311 0x11fd924 eliminate_with_rpo_vn(bitmap_head*) ../../gcc/gcc/tree-ssa-sccvn.cc:7504 0x1214664 do_rpo_vn_1 ../../gcc/gcc/tree-ssa-sccvn.cc:8616 0x1215ba5 execute ../../gcc/gcc/tree-ssa-sccvn.cc:8702 cc1 simplifies: lanes[0] = 0; lanes[1] = 0; lanes[2] = 0; lanes[3] = 0; _1 = { -1, ... }; _7 = svld1rq_u32 (_1, &lanes); to: _9 = MEM <vector(4) unsigned int> [(unsigned int * {ref-all})&lanes]; _7 = VEC_PERM_EXPR <_9, _9, { 0, 1, 2, 3, ... }>; and then fre1 dump shows: Applying pattern match.pd:8675, generic-match-5.cc:9025 Match-and-simplified VEC_PERM_EXPR <_9, _9, { 0, 1, 2, 3, ... }> to { 0, 0, 0, 0 } RHS VEC_PERM_EXPR <_9, _9, { 0, 1, 2, 3, ... }> simplified to { 0, 0, 0, 0 } The issue seems to be with the following pattern: (simplify (vec_perm vec_same_elem_p@0 @0 @1) @0) which simplifies above VEC_PERM_EXPR to: _7 = {0, 0, 0, 0} which is incorrect since _9 and mask have different vector lengths. The attached patch amends the pattern to simplify above VEC_PERM_EXPR only if operand and mask have same number of elements, which seems to fix the issue, and we're left with the following in .optimized dump: <bb 2> [local count: 1073741824]: _2 = VEC_PERM_EXPR <{ 0, 0, 0, 0 }, { 0, 0, 0, 0 }, { 0, 1, 2, 3, ... }>; return _2; code-gen: l: mov z0.b, #0 ret Patch is bootstrapped+tested on aarch64-linux-gnu. OK to commit ? Thanks, Prathamesh
[SVE][match.pd] Fix ICE observed in PR110280. gcc/ChangeLog: PR tree-optimization/110280 * match.pd (vec_perm_expr(v, v, mask) -> v): Simplify the pattern only if operand and mask of VEC_PERM_EXPR have same number of elements. gcc/testsuite/ChangeLog: * gcc.target/aarch64/sve/pr110280.c: New test. diff --git a/gcc/match.pd b/gcc/match.pd index 2dd23826034..0eb5f8f0af6 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -8669,10 +8669,11 @@ and, @0 (if (uniform_vector_p (@0)))) - (simplify (vec_perm vec_same_elem_p@0 @0 @1) - @0) + (if (known_eq (TYPE_VECTOR_SUBPARTS (TREE_TYPE (@0)), + TYPE_VECTOR_SUBPARTS (TREE_TYPE (@1)))) + @0)) /* Push VEC_PERM earlier if that may help FMA perception (PR101895). */ (simplify diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c b/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c new file mode 100644 index 00000000000..453c9cbcf9e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +#include "arm_sve.h" + +svuint32_t l() +{ + _Alignas(16) const unsigned int lanes[4] = {0, 0, 0, 0}; + return svld1rq_u32(svptrue_b8(), lanes); +}