> Just curious about the combine pass you mentioned, not very sure my
> understand is correct but it looks like the combine pass totally
> ignore the iterator requirement?
>
> It is sort of surprise to me as the combine pass may also need the
> information of iterators.
combine tries to match instructions (with fitting modes of course).
It does not look at the insn constraints that reload/lra later can
use to switch between alternatives depending on the register situation
and other factors.
We e.g. have an instruction
(define_insn "bla"
(set (match_operand:VF 1 "=vd")
(match_operand:VF 2 "vr"))
...
and implicitly
[(set_attr "enabled" "true")]
This instruction gets multiplexed via the VF iterator into (among others)
(define_insn "bla"
(set (match_operand:VNx4HF 1 "=vd")
(match_operand:VNx4HF 2 "vr"))
...
[(set_attr "enabled" "true")]
When we set "enabled" to "false" via "fp_vector_disabled", we have:
(define_insn "bla"
(set (match_operand:VNx4HF 1 "=vd")
(match_operand:VNx4HF 2 "vr"))
...
[(set_attr "enabled" "false")]
This means the only available alternative is disabled but the insn
itself is still there, particularly for combine which does not look
into the constraints.
So in our case the iterator "allowed" the instruction (leading combine
to think it is available) and we later masked it out with "enabled = false".
Now we could argue that combine's behavior should change here and an
insn without any alternatives is not actually available but that's not
a battle I'm willing to fight :D
Regards
Robin
