LGTM. Thanks for fixing this.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-07-05 21:00
To: gcc-patches; palmer; Kito Cheng; juzhe.zh...@rivai.ai; jeffreyalaw
CC: rdapp.gcc
Subject: [PATCH] RISC-V: Change truncate to float_truncate in narrowing
Hi,
Juzhe noticed that several floating-point conversion tests
FAIL on 32 bit. This is due to the autovect FP narrowing patterns
using a truncate instead of a float_truncate which results in
a combine ICE. It would try to e.g. simplify a unary operation by
simplify_const_unary_operation which obviously expects a float_truncate
and not a truncate for a floating-point mode.
Regards
Robin
gcc/ChangeLog:
* config/riscv/autovec.md: Use float_truncate.
---
gcc/config/riscv/autovec.md | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 466b27d5c49..3884dfc363c 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -473,7 +473,7 @@ (define_expand "extend<v_quad_trunc><mode>2"
;; -------------------------------------------------------------------------
(define_insn_and_split "trunc<mode><v_double_trunc>2"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vr")
- (truncate:<V_DOUBLE_TRUNC>
+ (float_truncate:<V_DOUBLE_TRUNC>
(match_operand:VWEXTF_ZVFHMIN 1 "register_operand" " vr")))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
@@ -493,7 +493,7 @@ (define_insn_and_split "trunc<mode><v_double_trunc>2"
;; -------------------------------------------------------------------------
(define_expand "trunc<mode><v_quad_trunc>2"
[(set (match_operand:<V_QUAD_TRUNC> 0 "register_operand")
- (truncate:<V_QUAD_TRUNC>
+ (float_truncate:<V_QUAD_TRUNC>
(match_operand:VQEXTF 1 "register_operand")))]
"TARGET_VECTOR && (TARGET_ZVFHMIN || TARGET_ZVFH)"
{
--
2.41.0
