On 7/10/23 2:18 PM, Carl Love wrote: > + /* Get the current FPSCR fields, bits 29:31 (DRN) and bits 56:63 (VE, OE, > UE, > + ZE, XE, NI, RN) from the FPSCR and return them. */
The 'Z' above should line up directly under the 'G' in Get. > - /* Insert new RN mode into FSCPR. */ > - emit_insn (gen_rs6000_mffs (tmp_df)); > - tmp_di = simplify_gen_subreg (DImode, tmp_df, DFmode, 0); > - emit_insn (gen_anddi3 (tmp_di, tmp_di, GEN_INT (-4))); > - emit_insn (gen_iordi3 (tmp_di, tmp_di, tmp_rn)); > + /* Insert the new RN value from tmp_rn into FPSCR bit [62:63]. */ > + emit_insn (gen_anddi3 (tmp_di1, tmp_di2, GEN_INT (-4))); > + emit_insn (gen_iordi3 (tmp_di1, tmp_di1, tmp_rn)); This is an expander, so you shouldn't reuse temporaries as multiple destination pseudos, since that limits the register allocator's freedom. I know the old code did it, but since you're changing the line, you might as well use a new temp. I cannot approve it, but it LGTM with those fixed. Peter
