> The recent change in TImode parameter passing on x86_64 results in the FAIL
> of pr91681-1.c. The issue is that with the extra flexibility, the combine
> pass is
> now spoilt for choice between using either the
> *add<dwi>3_doubleword_concat or the *add<dwi>3_doubleword_zext
> patterns, when one operand is a *concat and the other is a zero_extend.
> The solution proposed below is provide an
> *add<dwi>3_doubleword_concat_zext define_insn_and_split, that can
> benefit both from the register allocation of *concat, and still avoid the xor
> normally required by zero extension.
>
> I'm investigating a follow-up refinement to improve register allocation
> further by avoiding the early clobber in the =&r, and handling (custom)
> reloads explicitly, but this piece resolves the testcase failure.
>
> This patch has been tested on x86_64-pc-linux-gnu with make bootstrap and
> make -k check, both with and without --target_board=unix{-m32} with no
> new failures. Ok for mainline?
>
>
> 2023-07-11 Roger Sayle <ro...@nextmovesoftware.com>
>
> gcc/ChangeLog
> PR target/91681
> * config/i386/i386.md (*add<dwi>3_doubleword_concat_zext): New
> define_insn_and_split derived from *add<dwi>3_doubleword_concat
> and *add<dwi>3_doubleword_zext.
Hi Roger,
This commit currently changed the codegen of testcase p443644-2.c from:
movq %rdx, %rax
xorl %edx, %edx
addq %rdi, %rax
adcq %rsi, %rdx
to:
movq %rdx, %rcx
movq %rdi, %rax
movq %rsi, %rdx
addq %rcx, %rax
adcq $0, %rdx
which causes the testcase fail under -m64.
Is this within your expectation?
BRs,
Haochen
>
>
> Thanks,
> Roger
> --
