LGTM, thanks:)
Juzhe-Zhong <juzhe.zh...@rivai.ai> 於 2023年7月18日 週二 14:28 寫道：
> This patch is to dynamic adjust size of VLA vectors according to
> TARGET_MIN_VLEN (-march=*zvl*b).
>
> Currently, VNx16QImode is always [16,16] when TARGET_MINV_LEN >= 128.
>
> We are going to add a bunch of VLS modes (V16QI,V32QI,....etc), these
> modes should always be considered
> as having smaller size than VLA vectors.
>
> For example, the V32QImode is LMUL = 1 VLS mode when TARGET_MIN_VLEN = 256
> and V16QImode is LMUL = 1 VLS mode when TARGET_MINV_LEN = 128.
>
> Since a LMUL = 1 VLA mode VNx16QI is always [16,16] before this patch,
> when TARGET_MIN_VLEN = 128, VNx16QImode ([16,16]) > V16QImode.
> when TARGET_MIN_VLEN = 256, VNx16QImode ([16,16]) possible < V32QImode.
>
> Then such inconsistency (TARGET_MIN_VLEN = 128, regno_reg_rtx[97] is VLA
> modes wheras it is VLS modes when TARGET_MIN_VLEN = 256).
>
> This patch now adjust VLA vector size accurately according to
> TARGET_MIN_VLEN which make things more reasonable:
>
> VNx16QI = [16,16] if TARGET_MIN_VLEN = 128.
> VNx16QI = [32,32] if TARGET_MIN_VLEN = 256.
> VNx16QI = [64,64] if TARGET_MIN_VLEN = 512.
> VNx16QI = [128,128] if TARGET_MIN_VLEN = 1024.
> VNx16QI = [256,256] if TARGET_MIN_VLEN = 2048.
> VNx16QI = [512,512] if TARGET_MIN_VLEN = 4096.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-selftests.cc (run_poly_int_selftests): Add
> more selftests.
> * config/riscv/riscv.cc (riscv_legitimize_poly_move): Dynamic
> adjust size of VLA vectors.
> (riscv_convert_vector_bits): Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c: New test.
>
> ---
> gcc/config/riscv/riscv-selftests.cc | 10 +++++
> gcc/config/riscv/riscv.cc | 37 +++++++++++++------
> .../riscv/rvv/autovec/zve32f_zvl1024b-1.c | 6 +++
> .../riscv/rvv/autovec/zve32f_zvl2048b-1.c | 6 +++
> .../riscv/rvv/autovec/zve32f_zvl256b-1.c | 6 +++
> .../riscv/rvv/autovec/zve32f_zvl4096b-1.c | 6 +++
> .../riscv/rvv/autovec/zve32f_zvl512b-1.c | 6 +++
> .../riscv/rvv/autovec/zve32x_zvl1024b-1.c | 6 +++
> .../riscv/rvv/autovec/zve32x_zvl2048b-1.c | 6 +++
> .../riscv/rvv/autovec/zve32x_zvl256b-1.c | 6 +++
> .../riscv/rvv/autovec/zve32x_zvl4096b-1.c | 6 +++
> .../riscv/rvv/autovec/zve32x_zvl512b-1.c | 6 +++
> .../riscv/rvv/autovec/zve64d_zvl1024b-1.c | 6 +++
> .../riscv/rvv/autovec/zve64d_zvl2048b-1.c | 6 +++
> .../riscv/rvv/autovec/zve64d_zvl256b-1.c | 6 +++
> .../riscv/rvv/autovec/zve64d_zvl4096b-1.c | 6 +++
> .../riscv/rvv/autovec/zve64d_zvl512b-1.c | 6 +++
> .../riscv/rvv/autovec/zve64f_zvl1024b-1.c | 6 +++
> .../riscv/rvv/autovec/zve64f_zvl2048b-1.c | 6 +++
> .../riscv/rvv/autovec/zve64f_zvl256b-1.c | 6 +++
> .../riscv/rvv/autovec/zve64f_zvl4096b-1.c | 6 +++
> .../riscv/rvv/autovec/zve64f_zvl512b-1.c | 6 +++
> .../riscv/rvv/autovec/zve64x_zvl1024b-1.c | 6 +++
> .../riscv/rvv/autovec/zve64x_zvl2048b-1.c | 6 +++
> .../riscv/rvv/autovec/zve64x_zvl256b-1.c | 6 +++
> .../riscv/rvv/autovec/zve64x_zvl4096b-1.c | 6 +++
> .../riscv/rvv/autovec/zve64x_zvl512b-1.c | 6 +++
> 27 files changed, 185 insertions(+), 12 deletions(-)
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c
>
> diff --git a/gcc/config/riscv/riscv-selftests.cc
> b/gcc/config/riscv/riscv-selftests.cc
> index 1bf1a648fa1..b16b5c15286 100644
> --- a/gcc/config/riscv/riscv-selftests.cc
> +++ b/gcc/config/riscv/riscv-selftests.cc
> @@ -232,6 +232,16 @@ run_poly_int_selftests (void)
> worklist);
> run_poly_int_selftest ("rv32imafd_zve32x1p0", ABI_ILP32D,
> POLY_TEST_DIMODE,
> worklist);
> + simple_poly_selftest ("rv64imafdv_zvl256b", ABI_LP64D,
> + {QImode, HImode, SImode, DImode});
> + simple_poly_selftest ("rv64imafdv_zvl512b", ABI_LP64D,
> + {QImode, HImode, SImode, DImode});
> + simple_poly_selftest ("rv64imafdv_zvl1024b", ABI_LP64D,
> + {QImode, HImode, SImode, DImode});
> + simple_poly_selftest ("rv64imafdv_zvl2048b", ABI_LP64D,
> + {QImode, HImode, SImode, DImode});
> + simple_poly_selftest ("rv64imafdv_zvl4096b", ABI_LP64D,
> + {QImode, HImode, SImode, DImode});
> }
>
> static void
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index d51d6bd1aca..f1f5a73389e 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -2055,18 +2055,21 @@ riscv_legitimize_poly_move (machine_mode mode, rtx
> dest, rtx tmp, rtx src)
> riscv_emit_move (dest, GEN_INT (value.to_constant ()));
> return;
> }
> - else if ((factor % vlenb) == 0)
> - div_factor = 1;
> - else if ((factor % (vlenb / 2)) == 0)
> - div_factor = 2;
> - else if ((factor % (vlenb / 4)) == 0)
> - div_factor = 4;
> - else if ((factor % (vlenb / 8)) == 0)
> - div_factor = 8;
> - else if ((factor % (vlenb / 16)) == 0)
> - div_factor = 16;
> else
> - gcc_unreachable ();
> + {
> + /* FIXME: We currently DON'T support TARGET_MIN_VLEN > 4096. */
> + int max_power = exact_log2 (4096 / 128);
> + for (int i = 0; i < max_power; i++)
> + {
> + int possible_div_factor = 1 << i;
> + if (factor % (vlenb / possible_div_factor) == 0)
> + {
> + div_factor = possible_div_factor;
> + break;
> + }
> + }
> + gcc_assert (div_factor != 0);
> + }
>
> if (div_factor != 1)
> riscv_expand_op (LSHIFTRT, mode, tmp, tmp,
> @@ -6479,6 +6482,7 @@ riscv_init_machine_status (void)
> static poly_uint16
> riscv_convert_vector_bits (void)
> {
> + int chunk_num = 1;
> if (TARGET_MIN_VLEN >= 128)
> {
> /* We have Full 'V' extension for application processors. It's
> specified
> @@ -6486,6 +6490,15 @@ riscv_convert_vector_bits (void)
> and Zve64d extensions. Thus the number of bytes in a vector is 16
> + 16
> * x1 which is riscv_vector_chunks * 16 = poly_int (16, 16). */
> riscv_bytes_per_vector_chunk = 16;
> + /* Adjust BYTES_PER_RISCV_VECTOR according to TARGET_MIN_VLEN:
> + - TARGET_MIN_VLEN = 128bit: [16,16]
> + - TARGET_MIN_VLEN = 256bit: [32,32]
> + - TARGET_MIN_VLEN = 512bit: [64,64]
> + - TARGET_MIN_VLEN = 1024bit: [128,128]
> + - TARGET_MIN_VLEN = 2048bit: [256,256]
> + - TARGET_MIN_VLEN = 4096bit: [512,512]
> + FIXME: We currently DON'T support TARGET_MIN_VLEN > 4096bit. */
> + chunk_num = TARGET_MIN_VLEN / 128;
> }
> else if (TARGET_MIN_VLEN > 32)
> {
> @@ -6518,7 +6531,7 @@ riscv_convert_vector_bits (void)
> if (riscv_autovec_preference == RVV_FIXED_VLMAX)
> return (int) TARGET_MIN_VLEN / (riscv_bytes_per_vector_chunk * 8);
> else
> - return poly_uint16 (1, 1);
> + return poly_uint16 (chunk_num, chunk_num);
> }
> else
> return 1;
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c
> new file mode 100644
> index 00000000000..54a36ae72d2
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve32f_zvl1024b -mabi=ilp32d --param
> riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4
> "vect" } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c
> new file mode 100644
> index 00000000000..754aee23e91
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve32f_zvl2048b -mabi=ilp32d --param
> riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4
> "vect" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c
> new file mode 100644
> index 00000000000..52a2c2b42b1
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve32f_zvl256b -mabi=ilp32d --param
> riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4
> "vect" } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c
> new file mode 100644
> index 00000000000..7a911d154dd
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve32f_zvl4096b -mabi=ilp32d --param
> riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4
> "vect" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c
> new file mode 100644
> index 00000000000..8d26abbe130
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve32f_zvl512b -mabi=ilp32d --param
> riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4
> "vect" } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c
> new file mode 100644
> index 00000000000..15c481624ea
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve32x_zvl1024b -mabi=ilp32d --param
> riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2
> "vect" } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c
> new file mode 100644
> index 00000000000..46be1f4da5b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve32x_zvl2048b -mabi=ilp32d --param
> riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2
> "vect" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c
> new file mode 100644
> index 00000000000..90e30843be1
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve32x_zvl256b -mabi=ilp32d --param
> riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2
> "vect" } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c
> new file mode 100644
> index 00000000000..02ac73bcb05
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve32x_zvl4096b -mabi=ilp32d --param
> riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2
> "vect" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c
> new file mode 100644
> index 00000000000..50cbfe13175
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve32x_zvl512b -mabi=ilp32d --param
> riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2
> "vect" } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c
> new file mode 100644
> index 00000000000..013af76f5b4
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64d_zvl1024b -mabi=ilp32d --param
> riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 6
> "vect" } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c
> new file mode 100644
> index 00000000000..9cfcdf1fd5e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64d_zvl2048b -mabi=ilp32d --param
> riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 6
> "vect" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c
> new file mode 100644
> index 00000000000..e0c0aeaea9e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64d_zvl256b -mabi=ilp32d --param
> riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 6
> "vect" } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c
> new file mode 100644
> index 00000000000..b823e6342a7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64d_zvl4096b -mabi=ilp32d --param
> riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 6
> "vect" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c
> new file mode 100644
> index 00000000000..6824b74bcf1
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64d_zvl512b -mabi=ilp32d --param
> riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 6
> "vect" } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c
> new file mode 100644
> index 00000000000..cc4fabde5fe
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64f_zvl1024b -mabi=ilp32d --param
> riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5
> "vect" } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c
> new file mode 100644
> index 00000000000..5f9acbb44fd
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64f_zvl2048b -mabi=ilp32d --param
> riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5
> "vect" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c
> new file mode 100644
> index 00000000000..b3debc7399a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64f_zvl256b -mabi=ilp32d --param
> riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5
> "vect" } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c
> new file mode 100644
> index 00000000000..5f9acbb44fd
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64f_zvl2048b -mabi=ilp32d --param
> riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5
> "vect" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c
> new file mode 100644
> index 00000000000..6e99d37e2dd
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64f_zvl512b -mabi=ilp32d --param
> riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5
> "vect" } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c
> new file mode 100644
> index 00000000000..b3d17c48cab
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64x_zvl1024b -mabi=ilp32d --param
> riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3
> "vect" } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c
> new file mode 100644
> index 00000000000..b110771f191
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64x_zvl2048b -mabi=ilp32d --param
> riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3
> "vect" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c
> new file mode 100644
> index 00000000000..509d75ddb7c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64x_zvl256b -mabi=ilp32d --param
> riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3
> "vect" } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c
> new file mode 100644
> index 00000000000..0410eba4bdb
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64x_zvl4096b -mabi=ilp32d --param
> riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3
> "vect" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c
> new file mode 100644
> index 00000000000..2af91a249af
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64x_zvl512b -mabi=ilp32d --param
> riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3
> "vect" } } */
> --
> 2.36.1
>
>
