Re: [PATCH V3] RISC-V: Enable basic VLS modes support

[Kito Cheng via Gcc-patches]

Last minor thing :)

> +(define_insn_and_split "*mov<mode>"
> +  [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr")
> +       (match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" "  m,vr, vr"))]
> +  "TARGET_VECTOR"

Reject (set (mem) (mem)) by adding the check:

TARGET_VECTOR
&& (register_operand (operands[0], <VLS_AVL_REG:MODE>mode)
    || register_operand (operands[1], <VLS_AVL_REG:MODE>mode))"