Yes, looks there is some I missed after the last cleanup. I will have a double check after rounding API support.
Pan From: juzhe.zh...@rivai.ai <juzhe.zh...@rivai.ai> Sent: Thursday, August 3, 2023 9:40 AM To: Li, Pan2 <pan2...@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org> Cc: Li, Pan2 <pan2...@intel.com>; Wang, Yanzhang <yanzhang.w...@intel.com>; kito.cheng <kito.ch...@gmail.com> Subject: Re: [PATCH v1] RISC-V: Support RVV VFMUL rounding mode intrinsic API extern const function_base *const vfmul; -extern const function_base *const vfmul; +extern const function_base *const vfmul_frm; It seems that there is a redundant declaration in the original code? extern const function_base *const vfmul; -extern const function_base *const vfmul; ________________________________ juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai> From: pan2.li<mailto:pan2...@intel.com> Date: 2023-08-03 09:38 To: gcc-patches<mailto:gcc-patches@gcc.gnu.org> CC: juzhe.zhong<mailto:juzhe.zh...@rivai.ai>; pan2.li<mailto:pan2...@intel.com>; yanzhang.wang<mailto:yanzhang.w...@intel.com>; kito.cheng<mailto:kito.ch...@gmail.com> Subject: [PATCH v1] RISC-V: Support RVV VFMUL rounding mode intrinsic API From: Pan Li <pan2...@intel.com<mailto:pan2...@intel.com>> This patch would like to support the rounding mode API for the VFMUL for the below samples. * __riscv_vfmul_vv_f32m1_rm * __riscv_vfmul_vv_f32m1_rm_m * __riscv_vfmul_vf_f32m1_rm * __riscv_vfmul_vf_f32m1_rm_m Signed-off-by: Pan Li <pan2...@intel.com<mailto:pan2...@intel.com>> gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (vfmul_frm_obj): New declaration. (Base): Likewise. * config/riscv/riscv-vector-builtins-bases.h: Likewise. * config/riscv/riscv-vector-builtins-functions.def (vfmul_frm): New function definition. * config/riscv/vector.md: Add vfmul to frm_mode. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-single-mul.c: New test. --- .../riscv/riscv-vector-builtins-bases.cc | 3 ++ .../riscv/riscv-vector-builtins-bases.h | 2 +- .../riscv/riscv-vector-builtins-functions.def | 2 + gcc/config/riscv/vector.md | 2 +- .../riscv/rvv/base/float-point-single-mul.c | 44 +++++++++++++++++++ 5 files changed, 51 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-mul.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index ddf694c771c..3adc11138a3 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -277,6 +277,7 @@ public: /* Implements below instructions for now. - vfadd + - vfmul */ template<rtx_code CODE> class binop_frm : public function_base @@ -2103,6 +2104,7 @@ static CONSTEXPR const widen_binop_frm<PLUS> vfwadd_frm_obj; static CONSTEXPR const widen_binop<MINUS> vfwsub_obj; static CONSTEXPR const widen_binop_frm<MINUS> vfwsub_frm_obj; static CONSTEXPR const binop<MULT> vfmul_obj; +static CONSTEXPR const binop_frm<MULT> vfmul_frm_obj; static CONSTEXPR const binop<DIV> vfdiv_obj; static CONSTEXPR const reverse_binop<DIV> vfrdiv_obj; static CONSTEXPR const widen_binop<MULT> vfwmul_obj; @@ -2334,6 +2336,7 @@ BASE (vfwadd_frm) BASE (vfwsub) BASE (vfwsub_frm) BASE (vfmul) +BASE (vfmul_frm) BASE (vfdiv) BASE (vfrdiv) BASE (vfwmul) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index 5800fca0169..9c12a6b4e8f 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -152,7 +152,7 @@ extern const function_base *const vfwadd_frm; extern const function_base *const vfwsub; extern const function_base *const vfwsub_frm; extern const function_base *const vfmul; -extern const function_base *const vfmul; +extern const function_base *const vfmul_frm; extern const function_base *const vfdiv; extern const function_base *const vfrdiv; extern const function_base *const vfwmul; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index 58a7224fe0c..35a83ef239c 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -319,6 +319,8 @@ DEF_RVV_FUNCTION (vfmul, alu, full_preds, f_vvf_ops) DEF_RVV_FUNCTION (vfdiv, alu, full_preds, f_vvv_ops) DEF_RVV_FUNCTION (vfdiv, alu, full_preds, f_vvf_ops) DEF_RVV_FUNCTION (vfrdiv, alu, full_preds, f_vvf_ops) +DEF_RVV_FUNCTION (vfmul_frm, alu_frm, full_preds, f_vvv_ops) +DEF_RVV_FUNCTION (vfmul_frm, alu_frm, full_preds, f_vvf_ops) // 13.5. Vector Widening Floating-Point Multiply DEF_RVV_FUNCTION (vfwmul, alu, full_preds, f_wvv_ops) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 65f36744f54..5d3e4256cd5 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -866,7 +866,7 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none" ;; Defines rounding mode of an floating-point operation. (define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none" - (cond [(eq_attr "type" "vfalu,vfwalu") + (cond [(eq_attr "type" "vfalu,vfwalu,vfmul") (cond [(match_test "INTVAL (operands[9]) == riscv_vector::FRM_RNE") (const_string "rne") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-mul.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-mul.c new file mode 100644 index 00000000000..e6410ea3a37 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-mul.c @@ -0,0 +1,44 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +typedef float float32_t; + +vfloat32m1_t +test_riscv_vfmul_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { + return __riscv_vfmul_vv_f32m1_rm (op1, op2, 0, vl); +} + +vfloat32m1_t +test_vfmul_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfmul_vv_f32m1_rm_m (mask, op1, op2, 1, vl); +} + +vfloat32m1_t +test_vfmul_vf_f32m1_rm (vfloat32m1_t op1, float32_t op2, size_t vl) { + return __riscv_vfmul_vf_f32m1_rm (op1, op2, 2, vl); +} + +vfloat32m1_t +test_vfmul_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2, + size_t vl) { + return __riscv_vfmul_vf_f32m1_rm_m (mask, op1, op2, 3, vl); +} + +vfloat32m1_t +test_riscv_vfmul_vv_f32m1 (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { + return __riscv_vfmul_vv_f32m1 (op1, op2, vl); +} + +vfloat32m1_t +test_vfmul_vv_f32m1_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfmul_vv_f32m1_m (mask, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfmul\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 6 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */ -- 2.34.1
