+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[8])"))])
I don't think we need "(enum attr_frm_mode)"
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-08-06 11:36
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode
intrinsic
From: Pan Li <pan2...@intel.com>
The frm_mode attr has some assumptions for each define insn as below.
1. The define insn has at least 9 operands.
2. The operands[9] must be frm reg.
3. The operands[9] must be const int.
Actually, the frm operand can be operands[8], operands[9] or
operands[10], and not all the define insn has frm operands.
This patch would like to refactor frm and eliminate the above
assumptions, as well as unblock the underlying rounding mode intrinsic
API support.
After refactor, the default frm will be none, and the selected insn type
will be dyn. For the floating point which honors the frm, we will
set the frm_mode attr explicitly in define_insn.
Passed both the riscv.exp and rvv.exp for rv32/rv64 tests.
Signed-off-by: Pan Li <pan2...@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-protos.h (get_frm_mode): Remove operand
assumptions.
* config/riscv/riscv-v.cc (get_frm_mode): New function.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_ternop_insn):
* config/riscv/vector.md: Set frm_mode attr explicitly.
---
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-v.cc | 28 ++++
gcc/config/riscv/riscv-vector-builtins.cc | 22 ++-
gcc/config/riscv/vector.md | 170 ++++++++++++++--------
4 files changed, 159 insertions(+), 62 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 324991e2619..33f7cb1d670 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -236,6 +236,7 @@ bool check_builtin_call (location_t, vec<location_t>,
unsigned int,
tree, unsigned int, tree *);
bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
bool legitimize_move (rtx, rtx);
+int get_frm_mode (rtx);
void emit_vlmax_vsetvl (machine_mode, rtx);
void emit_hard_vlmax_vsetvl (machine_mode, rtx);
void emit_vlmax_insn (unsigned, int, rtx *, rtx = 0);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 278452b9e05..d5fb8611d6e 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1513,6 +1513,34 @@ expand_const_vector (rtx target, rtx src)
gcc_unreachable ();
}
+/* Get the frm mode with given CONST_INT rtx, the default mode is
+ FRM_MODE_DYN. */
+int
+get_frm_mode (rtx operand)
+{
+ gcc_assert (CONST_INT_P (operand));
+
+ switch (INTVAL (operand))
+ {
+ case FRM_RNE:
+ return FRM_MODE_RNE;
+ case FRM_RTZ:
+ return FRM_MODE_RTZ;
+ case FRM_RDN:
+ return FRM_MODE_RDN;
+ case FRM_RUP:
+ return FRM_MODE_RUP;
+ case FRM_RMM:
+ return FRM_MODE_RMM;
+ case FRM_DYN:
+ return FRM_MODE_DYN;
+ default:
+ return FRM_MODE_DYN;
+ }
+
+ gcc_unreachable ();
+}
+
/* Expand a pre-RA RVV data move from SRC to DEST.
It expands move for RVV fractional vector modes. */
bool
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
b/gcc/config/riscv/riscv-vector-builtins.cc
index 528dca7ae85..abab06c00ed 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3730,17 +3730,29 @@ function_expander::use_ternop_insn (bool vd_accum_p,
insn_code icode)
}
for (int argno = arg_offset; argno < call_expr_nargs (exp); argno++)
- add_input_operand (argno);
+ {
+ if (base->has_rounding_mode_operand_p ()
+ && argno == call_expr_nargs (exp) - 2)
+ {
+ /* Since the rounding mode argument position is not consistent with
+ the instruction pattern, we need to skip rounding mode argument
+ here. */
+ continue;
+ }
+ add_input_operand (argno);
+ }
add_input_operand (Pmode, get_tail_policy_for_pred (pred));
add_input_operand (Pmode, get_mask_policy_for_pred (pred));
add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX));
- /* TODO: Currently, we don't support intrinsic that is modeling rounding
mode.
- We add default rounding mode for the intrinsics that didn't model rounding
- mode yet. */
+ if (base->has_rounding_mode_operand_p ())
+ add_input_operand (call_expr_nargs (exp) - 2);
+
+ /* The RVV floating-point only support dynamic rounding mode in the
+ FRM register. */
if (opno != insn_data[icode].n_generator_args)
- add_input_operand (Pmode, const0_rtx);
+ add_input_operand (Pmode, gen_int_mode (riscv_vector::FRM_DYN, Pmode));
return generate_insn (icode);
}
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 750b2de8df9..db3ee105ef4 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -867,26 +867,8 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
;; Defines rounding mode of an floating-point operation.
(define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none"
(cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul")
- (cond
- [(match_test "INTVAL (operands[9]) == riscv_vector::FRM_RNE")
- (const_string "rne")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RTZ")
- (const_string "rtz")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RDN")
- (const_string "rdn")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RUP")
- (const_string "rup")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RMM")
- (const_string "rmm")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_DYN")
- (const_string "dyn")]
- (const_string "none"))]
- (const_string "none")))
+ (const_string "dyn")]
+ (const_string "none")))
;; -----------------------------------------------------------------
;; ---- Miscellaneous Operations
@@ -6147,7 +6129,9 @@ (define_insn "@pred_<optab><mode>"
"TARGET_VECTOR"
"vf<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[9])"))])
(define_insn "@pred_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6190,7 +6174,9 @@ (define_insn "@pred_<optab><mode>_scalar"
"TARGET_VECTOR"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[9])"))])
(define_insn "@pred_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6234,7 +6220,9 @@ (define_insn "@pred_<optab><mode>_scalar"
"TARGET_VECTOR"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[9])"))])
(define_insn "@pred_<optab><mode>_reverse_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6257,7 +6245,9 @@ (define_insn "@pred_<optab><mode>_reverse_scalar"
"TARGET_VECTOR"
"vfr<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[9])"))])
(define_insn "@pred_<copysign><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6408,7 +6398,9 @@ (define_insn "*pred_<madd_msub><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[9])"))])
(define_insn "*pred_<macc_msac><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6441,7 +6433,9 @@ (define_insn "*pred_<macc_msac><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[9])"))])
(define_insn_and_rewrite "*pred_mul_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6478,7 +6472,9 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>"
operands[5] = operands[4] = operands[0];
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[10])"))])
(define_expand "@pred_mul_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand")
@@ -6535,7 +6531,9 @@ (define_insn "*pred_<madd_msub><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[9])"))])
(define_insn "*pred_<macc_msac><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr,
?&vr")
@@ -6569,7 +6567,9 @@ (define_insn "*pred_<macc_msac><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[9])"))])
(define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6606,7 +6606,9 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
operands[5] = operands[4] = operands[0];
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[10])"))])
(define_expand "@pred_mul_neg_<optab><mode>"
[(set (match_operand:VF 0 "register_operand")
@@ -6668,7 +6670,9 @@ (define_insn "*pred_<nmsub_nmadd><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[9])"))])
(define_insn "*pred_<nmsac_nmacc><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6702,7 +6706,9 @@ (define_insn "*pred_<nmsac_nmacc><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[9])"))])
(define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6740,7 +6746,9 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
operands[5] = operands[4] = operands[0];
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[10])"))])
(define_expand "@pred_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand")
@@ -6799,7 +6807,9 @@ (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[9])"))])
(define_insn "*pred_<nmsac_nmacc><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr,
?&vr")
@@ -6834,7 +6844,9 @@ (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[9])"))])
(define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6872,7 +6884,9 @@ (define_insn_and_rewrite
"*pred_mul_neg_<optab><mode>_scalar"
operands[5] = operands[4] = operands[0];
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[10])"))])
;;
-------------------------------------------------------------------------------
;; ---- Predicated floating-point unary operations
@@ -6908,7 +6922,9 @@ (define_insn "@pred_<optab><mode>"
(set_attr "vl_op_idx" "4")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[8])"))])
(define_insn "@pred_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -7002,7 +7018,9 @@ (define_insn "@pred_dual_widen_<optab><mode>"
"TARGET_VECTOR"
"vfw<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[9])"))])
(define_insn "@pred_dual_widen_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr,
&vr")
@@ -7027,7 +7045,9 @@ (define_insn "@pred_dual_widen_<optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[9])"))])
(define_insn "@pred_single_widen_add<mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr,
&vr")
@@ -7050,7 +7070,9 @@ (define_insn "@pred_single_widen_add<mode>"
"TARGET_VECTOR"
"vfwadd.wv\t%0,%3,%4%p1"
[(set_attr "type" "vfwalu")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[9])"))])
(define_insn "@pred_single_widen_sub<mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr,
&vr")
@@ -7073,7 +7095,9 @@ (define_insn "@pred_single_widen_sub<mode>"
"TARGET_VECTOR"
"vfwsub.wv\t%0,%3,%4%p1"
[(set_attr "type" "vfwalu")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[9])"))])
(define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr,
&vr")
@@ -7097,7 +7121,9 @@ (define_insn
"@pred_single_widen_<plus_minus:optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<insn>.wf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[9])"))])
;;
-------------------------------------------------------------------------------
;; ---- Predicated widen floating-point ternary operations
@@ -7130,7 +7156,9 @@ (define_insn "@pred_widen_mul_<optab><mode>"
"TARGET_VECTOR"
"vfw<macc_msac>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[9])"))])
(define_insn "@pred_widen_mul_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7157,7 +7185,9 @@ (define_insn "@pred_widen_mul_<optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<macc_msac>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[9])"))])
(define_insn "@pred_widen_mul_neg_<optab><mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7184,7 +7214,9 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>"
"TARGET_VECTOR"
"vfw<nmsac_nmacc>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[9])"))])
(define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7212,7 +7244,9 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[9])"))])
;;
-------------------------------------------------------------------------------
;; ---- Predicated floating-point comparison operations
@@ -7522,7 +7556,9 @@ (define_insn "@pred_fcvt_x<v_su>_f<mode>"
"TARGET_VECTOR"
"vfcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfcvtftoi")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[8])"))])
(define_insn "@pred_<fix_cvt><mode>"
[(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd, vr, vr")
@@ -7562,7 +7598,9 @@ (define_insn "@pred_<float_cvt><mode>"
"TARGET_VECTOR"
"vfcvt.f.x<u>.v\t%0,%3%p1"
[(set_attr "type" "vfcvtitof")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[8])"))])
;;
-------------------------------------------------------------------------------
;; ---- Predicated floating-point widen conversions
@@ -7590,7 +7628,9 @@ (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
"TARGET_VECTOR"
"vfwcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftoi")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[8])"))])
(define_insn "@pred_widen_<fix_cvt><mode>"
[(set (match_operand:VWCONVERTI 0 "register_operand" "=&vr, &vr")
@@ -7675,7 +7715,9 @@ (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
"TARGET_VECTOR"
"vfncvt.x<v_su>.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftoi")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[8])"))])
(define_insn "@pred_narrow_<fix_cvt><mode>"
[(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr,
vr, &vr, &vr")
@@ -7715,7 +7757,9 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
"TARGET_VECTOR"
"vfncvt.f.x<u>.w\t%0,%3%p1"
[(set_attr "type" "vfncvtitof")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[8])"))])
(define_insn "@pred_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd,
vr, vr, &vr, &vr")
@@ -7736,7 +7780,9 @@ (define_insn "@pred_trunc<mode>"
"TARGET_VECTOR"
"vfncvt.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[8])"))])
(define_insn "@pred_rod_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd,
vr, vr, &vr, &vr")
@@ -8016,7 +8062,9 @@ (define_insn
"@pred_reduc_plus<order><VHF:mode><VHF_LMUL1:mode>"
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VHF:MODE>")])
+ (set_attr "mode" "<VHF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[8])"))])
;; Float Ordered Reduction Sum for SF
(define_insn "@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>"
@@ -8042,7 +8090,9 @@ (define_insn
"@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>"
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VSF:MODE>")])
+ (set_attr "mode" "<VSF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[8])"))])
;; Float Ordered Reduction Sum for DF
(define_insn "@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>"
@@ -8068,7 +8118,9 @@ (define_insn
"@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>"
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VDF:MODE>")])
+ (set_attr "mode" "<VDF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[8])"))])
;; Float Widen Reduction for HF, aka SF = HF op SF
(define_insn "@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>"
@@ -8090,7 +8142,9 @@ (define_insn
"@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>"
"TARGET_VECTOR"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
- (set_attr "mode" "<VHF:MODE>")])
+ (set_attr "mode" "<VHF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[8])"))])
;; Float Widen Reduction for SF, aka DF = SF * DF
(define_insn "@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>"
@@ -8112,7 +8166,9 @@ (define_insn
"@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>"
"TARGET_VECTOR"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
- (set_attr "mode" "<VSF:MODE>")])
+ (set_attr "mode" "<VSF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode
(operands[8])"))])
;;
-------------------------------------------------------------------------------
;; ---- Predicated permutation operations
--
2.34.1
