On Tue, Aug 08, 2023 at 03:13:09PM +0800, Haochen Jiang via Gcc-patches wrote: > We will send out our initial support of AVX10 and some sample patches in this > mailing thread. And there will be more coming up afterwards. Therefore, we > would > like to share our proposed AVX10 design in GCC. > > Here is a quick introduction to AVX10: > - AVX10 is the first major new ISA since the introduction of AVX512 in 2013. > - Since the introduction of AVX10, we would like to establish a common, > converged vector instruction set across all Intel architectures, including > Xeon Server, Atom Server and Clients. > - The default maximum vector size for AVX10 will be 256 bit, while 512 bit > is > optional.
So, what does this imply for the current ISAs? The expectations in lots of config/i386/* is that -mavx512f / TARGET_AVX512F means 512 bit vector support is available and most of the various -mavx512XXX options imply -mavx512f (and -mno-avx512f turns those off). And if -mavx512vl / TARGET_AVX512VL isn't available, tons of places just use 512-bit EVEX instructions for 256-bit or 128-bit stuff (mostly to be able to access [xy]mm16+). Sure, I expect all AVX10.N CPUs will have AVX512VL CPUID, will they have AVX512F CPUID even when the 512-bit vectors aren't present? What happens if one mixes the -mavx10* options together with -mno-avx512vl or similar options? Will -mno-avx512f still imply -mno-avx512vl etc.? Jakub