On 8/4/23 08:05, Wilco Dijkstra via Gcc-patches wrote:
+#ifdef HWCAP_USCAT + +#define MIDR_IMPLEMENTOR(midr) (((midr) >> 24) & 255) +#define MIDR_PARTNUM(midr) (((midr) >> 4) & 0xfff) + +static inline bool +ifunc1 (unsigned long hwcap) +{ + if (hwcap & HWCAP_USCAT) + return true; + if (!(hwcap & HWCAP_CPUID)) + return false; + + unsigned long midr; + asm volatile ("mrs %0, midr_el1" : "=r" (midr)); + + /* Neoverse N1 supports atomic 128-bit load/store. */ + if (MIDR_IMPLEMENTOR (midr) == 'A' && MIDR_PARTNUM(midr) == 0xd0c) + return true; + + return false; +} +#endif
Why would HWCAP_USCAT not be set by the kernel? Failing that, I would think you would check ID_AA64MMFR2_EL1.AT. r~