Committed, thanks Juzhe. Pan
From: juzhe.zh...@rivai.ai <juzhe.zh...@rivai.ai> Sent: Friday, August 11, 2023 6:24 PM To: Li, Pan2 <pan2...@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org> Cc: jeffreyalaw <jeffreya...@gmail.com>; Li, Pan2 <pan2...@intel.com>; Wang, Yanzhang <yanzhang.w...@intel.com>; kito.cheng <kito.ch...@gmail.com> Subject: Re: [PATCH v1] RISC-V: Support RVV VFMSUB rounding mode intrinsic API LGTM ________________________________ juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai> From: pan2.li<mailto:pan2...@intel.com> Date: 2023-08-11 18:11 To: gcc-patches<mailto:gcc-patches@gcc.gnu.org> CC: juzhe.zhong<mailto:juzhe.zh...@rivai.ai>; jeffreyalaw<mailto:jeffreya...@gmail.com>; pan2.li<mailto:pan2...@intel.com>; yanzhang.wang<mailto:yanzhang.w...@intel.com>; kito.cheng<mailto:kito.ch...@gmail.com> Subject: [PATCH v1] RISC-V: Support RVV VFMSUB rounding mode intrinsic API From: Pan Li <pan2...@intel.com<mailto:pan2...@intel.com>> This patch would like to support the rounding mode API for the VFMSUB as the below samples. * __riscv_vfmsub_vv_f32m1_rm * __riscv_vfmsub_vv_f32m1_rm_m * __riscv_vfmsub_vf_f32m1_rm * __riscv_vfmsub_vf_f32m1_rm_m Signed-off-by: Pan Li <pan2...@intel.com<mailto:pan2...@intel.com>> gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class vfmsub_frm): New class for vfmsub frm. (vfmsub_frm): New declaration. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vfmsub_frm): New function declaration. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-msub.c: New test. --- .../riscv/riscv-vector-builtins-bases.cc | 25 ++++++++++ .../riscv/riscv-vector-builtins-bases.h | 1 + .../riscv/riscv-vector-builtins-functions.def | 2 + .../riscv/rvv/base/float-point-msub.c | 47 +++++++++++++++++++ 4 files changed, 75 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msub.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index b085ba4f52d..381bc72c784 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -493,6 +493,29 @@ public: } }; +/* Implements below instructions for frm + - vfmsub +*/ +class vfmsub_frm : public function_base +{ +public: + bool has_rounding_mode_operand_p () const override { return true; } + + bool has_merge_operand_p () const override { return false; } + + rtx expand (function_expander &e) const override + { + if (e.op_info->op == OP_TYPE_vf) + return e.use_ternop_insn ( + false, code_for_pred_mul_scalar (MINUS, e.vector_mode ())); + if (e.op_info->op == OP_TYPE_vv) + return e.use_ternop_insn ( + false, code_for_pred_mul (MINUS, e.vector_mode ())); + + gcc_unreachable (); + } +}; + /* Implements vrsub. */ class vrsub : public function_base { @@ -2266,6 +2289,7 @@ static CONSTEXPR const vfmsac_frm vfmsac_frm_obj; static CONSTEXPR const vfnmadd vfnmadd_obj; static CONSTEXPR const vfnmadd_frm vfnmadd_frm_obj; static CONSTEXPR const vfmsub vfmsub_obj; +static CONSTEXPR const vfmsub_frm vfmsub_frm_obj; static CONSTEXPR const vfwmacc vfwmacc_obj; static CONSTEXPR const vfwnmacc vfwnmacc_obj; static CONSTEXPR const vfwmsac vfwmsac_obj; @@ -2507,6 +2531,7 @@ BASE (vfmsac_frm) BASE (vfnmadd) BASE (vfnmadd_frm) BASE (vfmsub) +BASE (vfmsub_frm) BASE (vfwmacc) BASE (vfwnmacc) BASE (vfwmsac) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index 4ade0ace7b2..99cfbfd78c8 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -173,6 +173,7 @@ extern const function_base *const vfmsac_frm; extern const function_base *const vfnmadd; extern const function_base *const vfnmadd_frm; extern const function_base *const vfmsub; +extern const function_base *const vfmsub_frm; extern const function_base *const vfwmacc; extern const function_base *const vfwnmacc; extern const function_base *const vfwmsac; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index e9b16f99180..75235ec01d3 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -361,6 +361,8 @@ DEF_RVV_FUNCTION (vfmadd_frm, alu_frm, full_preds, f_vvvv_ops) DEF_RVV_FUNCTION (vfmadd_frm, alu_frm, full_preds, f_vvfv_ops) DEF_RVV_FUNCTION (vfnmadd_frm, alu_frm, full_preds, f_vvvv_ops) DEF_RVV_FUNCTION (vfnmadd_frm, alu_frm, full_preds, f_vvfv_ops) +DEF_RVV_FUNCTION (vfmsub_frm, alu_frm, full_preds, f_vvvv_ops) +DEF_RVV_FUNCTION (vfmsub_frm, alu_frm, full_preds, f_vvfv_ops) // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msub.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msub.c new file mode 100644 index 00000000000..e58519d0742 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msub.c @@ -0,0 +1,47 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +typedef float float32_t; + +vfloat32m1_t +test_riscv_vfmsub_vv_f32m1_rm (vfloat32m1_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmsub_vv_f32m1_rm (vd, op1, op2, 0, vl); +} + +vfloat32m1_t +test_vfmsub_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmsub_vv_f32m1_rm_m (mask, vd, op1, op2, 1, vl); +} + +vfloat32m1_t +test_vfmsub_vf_f32m1_rm (vfloat32m1_t vd, float32_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfmsub_vf_f32m1_rm (vd, op1, op2, 2, vl); +} + +vfloat32m1_t +test_vfmsub_vf_f32m1_rm_m (vfloat32m1_t vd, vbool32_t mask, float32_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmsub_vf_f32m1_rm_m (mask, vd, op1, op2, 3, vl); +} + +vfloat32m1_t +test_riscv_vfmsub_vv_f32m1 (vfloat32m1_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmsub_vv_f32m1 (vd, op1, op2, vl); +} + +vfloat32m1_t +test_vfmsub_vv_f32m1_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmsub_vv_f32m1_m (mask, vd, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfmsub\.v[vf]\s+v[0-9]+,\s*[fav]+[0-9]+,\s*v[0-9]+} 6 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */ -- 2.34.1
