Committed, thanks Juzhe. Pan
From: juzhe.zh...@rivai.ai <juzhe.zh...@rivai.ai> Sent: Monday, August 14, 2023 3:03 PM To: Li, Pan2 <pan2...@intel.com> Cc: gcc-patches <gcc-patches@gcc.gnu.org>; kito.cheng <kito.ch...@gmail.com> Subject: Re: FW: [PATCH v1] RISC-V: Support RVV VFWNMACC rounding mode intrinsic API LGTM ________________________________ juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai> From: Li, Pan2<mailto:pan2...@intel.com> Date: 2023-08-14 15:01 To: juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai> Subject: FW: [PATCH v1] RISC-V: Support RVV VFWNMACC rounding mode intrinsic API Kindly ping. Pan -----Original Message----- From: Li, Pan2 <pan2...@intel.com<mailto:pan2...@intel.com>> Sent: Monday, August 14, 2023 10:36 AM To: gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org> Cc: juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>; Li, Pan2 <pan2...@intel.com<mailto:pan2...@intel.com>>; Wang, Yanzhang <yanzhang.w...@intel.com<mailto:yanzhang.w...@intel.com>>; kito.ch...@gmail.com<mailto:kito.ch...@gmail.com> Subject: [PATCH v1] RISC-V: Support RVV VFWNMACC rounding mode intrinsic API From: Pan Li <pan2...@intel.com<mailto:pan2...@intel.com>> This patch would like to support the rounding mode API for the VFWNMACC as the below samples. * __riscv_vfwnmacc_vv_f64m2_rm * __riscv_vfwnmacc_vv_f64m2_rm_m * __riscv_vfwnmacc_vf_f64m2_rm * __riscv_vfwnmacc_vf_f64m2_rm_m Signed-off-by: Pan Li <pan2...@intel.com<mailto:pan2...@intel.com>> gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class vfwnmacc_frm): New class for frm. (vfwnmacc_frm_obj): New declaration. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vfwnmacc_frm): New intrinsic function definition. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-wnmacc.c: New test. --- .../riscv/riscv-vector-builtins-bases.cc | 25 ++++++++++ .../riscv/riscv-vector-builtins-bases.h | 1 + .../riscv/riscv-vector-builtins-functions.def | 2 + .../riscv/rvv/base/float-point-wnmacc.c | 47 +++++++++++++++++++ 4 files changed, 75 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wnmacc.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index e84d6d1d047..4a7f2b8e3e9 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -562,6 +562,29 @@ public: } }; +/* Implements below instructions for frm + - vfwnmacc +*/ +class vfwnmacc_frm : public function_base +{ +public: + bool has_rounding_mode_operand_p () const override { return true; } + + bool has_merge_operand_p () const override { return false; } + + rtx expand (function_expander &e) const override + { + if (e.op_info->op == OP_TYPE_vf) + return e.use_widen_ternop_insn ( + code_for_pred_widen_mul_neg_scalar (MINUS, e.vector_mode ())); + if (e.op_info->op == OP_TYPE_vv) + return e.use_widen_ternop_insn ( + code_for_pred_widen_mul_neg (MINUS, e.vector_mode ())); + + gcc_unreachable (); + } +}; + /* Implements vrsub. */ class vrsub : public function_base { @@ -2340,6 +2363,7 @@ static CONSTEXPR const vfmsub_frm vfmsub_frm_obj; static CONSTEXPR const vfwmacc vfwmacc_obj; static CONSTEXPR const vfwmacc_frm vfwmacc_frm_obj; static CONSTEXPR const vfwnmacc vfwnmacc_obj; +static CONSTEXPR const vfwnmacc_frm vfwnmacc_frm_obj; static CONSTEXPR const vfwmsac vfwmsac_obj; static CONSTEXPR const vfwnmsac vfwnmsac_obj; static CONSTEXPR const unop<SQRT> vfsqrt_obj; @@ -2584,6 +2608,7 @@ BASE (vfmsub_frm) BASE (vfwmacc) BASE (vfwmacc_frm) BASE (vfwnmacc) +BASE (vfwnmacc_frm) BASE (vfwmsac) BASE (vfwnmsac) BASE (vfsqrt) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index acbc7d42fbe..27c7deb4ec2 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -178,6 +178,7 @@ extern const function_base *const vfmsub_frm; extern const function_base *const vfwmacc; extern const function_base *const vfwmacc_frm; extern const function_base *const vfwnmacc; +extern const function_base *const vfwnmacc_frm; extern const function_base *const vfwmsac; extern const function_base *const vfwnmsac; extern const function_base *const vfsqrt; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index 0b73a5bcbc5..481c3b899f2 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -378,6 +378,8 @@ DEF_RVV_FUNCTION (vfwnmsac, alu, full_preds, f_wwfv_ops) DEF_RVV_FUNCTION (vfwmacc_frm, alu_frm, full_preds, f_wwvv_ops) DEF_RVV_FUNCTION (vfwmacc_frm, alu_frm, full_preds, f_wwfv_ops) +DEF_RVV_FUNCTION (vfwnmacc_frm, alu_frm, full_preds, f_wwvv_ops) +DEF_RVV_FUNCTION (vfwnmacc_frm, alu_frm, full_preds, f_wwfv_ops) // 13.8. Vector Floating-Point Square-Root Instruction DEF_RVV_FUNCTION (vfsqrt, alu, full_preds, f_v_ops) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wnmacc.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wnmacc.c new file mode 100644 index 00000000000..2602289ec88 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wnmacc.c @@ -0,0 +1,47 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +typedef float float32_t; + +vfloat64m2_t +test_vfwnmacc_vv_f32m1_rm (vfloat64m2_t vd, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfwnmacc_vv_f64m2_rm (vd, op1, op2, 0, vl); +} + +vfloat64m2_t +test_vfwnmacc_vv_f32m1_rm_m (vbool32_t mask, vfloat64m2_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfwnmacc_vv_f64m2_rm_m (mask, vd, op1, op2, 1, vl); +} + +vfloat64m2_t +test_vfwnmacc_vf_f32m1_rm (vfloat64m2_t vd, float32_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfwnmacc_vf_f64m2_rm (vd, op1, op2, 2, vl); +} + +vfloat64m2_t +test_vfwnmacc_vf_f32m1_rm_m (vbool32_t mask, vfloat64m2_t vd, float32_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfwnmacc_vf_f64m2_rm_m (mask, vd, op1, op2, 3, vl); +} + +vfloat64m2_t +test_vfwnmacc_vv_f32m1 (vfloat64m2_t vd, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfwnmacc_vv_f64m2 (vd, op1, op2, vl); +} + +vfloat64m2_t +test_vfwnmacc_vv_f32m1_m (vbool32_t mask, vfloat64m2_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfwnmacc_vv_f64m2_m (mask, vd, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfwnmacc\.[vw][vf]\s+v[0-9]+,\s*[fav]+[0-9]+,\s*[fav]+[0-9]+} 6 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */ -- 2.34.1
