Hi Carl,

on 2023/8/9 23:52, Carl Love wrote:
> 
> GCC maintainers:
> 
> The following patch adds four built-ins for the decimal floating point
> (DFP) quantize instructions on rs6000.  The built-ins are for 64-bit
> and 128-bit DFP operands.
> 
> The patch also adds a test case for the new builtins.
> 
> The Patch has been tested on Power 10LE and Power 9 LE/BE.
> 
> Please let me know if the patch is acceptable for mainline.  Thanks.
> 
>                  Carl Love
> 
> 
> ------------------------------------------
> rs6000, add overloaded DFP quantize support
> 
> Add decimal floating point (DFP) quantize built-ins for both 64-bit DFP
> and 128-DFP operands.  In each case, there is an immediate version and a
> variable version of the bult-in.  The RM value is a 2-bit const int which

Nit: s/bult-in//built-in/

> specifies the rounding mode to use.  For the immediate versions of the
> built-in, TE field is a 5-bit constant that specifies the value of the
> ideal exponent for the result.  The built-in specifications are:
> 
>   __Decimal64 builtin_dfp_quantize (_Decimal64, _Decimal64,
>                                   const int RM)
>   __Decimal64 builtin_dfp_quantize (const int TE, _Decimal64,
>                                   const int)
>   __Decimal128 builtin_dfpq_quantize (_Decimal128, _Decimal128,
>                                     const int RM)
>   __Decimal128 builtin_dfpq_quantize (const int TE, _Decimal128,
>                                     const int)
> 

I noticed that the existing DFP bifs are directly using the insn
mnemonics, I perfer to keep consistent with them.  So could we
have one function like unique external interface like dfp_quantize
for users' uses?

And we can have the underlying instances for it:

__Decimal64 builtin_dfp_dqua (_Decimal64, _Decimal64, const int RM)

__Decimal64 builtin_dfp_dquai (const int TE, _Decimal64, const int)

__Decimal128 builtin_dfp_dquaq (_Decimal128, _Decimal128, const int RM)

__Decimal128 builtin_dfp_dquaiq (const int TE, _Decimal128, const int)

Besides, this patch missed to update the documentation, please add them
in gcc//doc/extend.texi by searching "The following built-in functions
are available when hardware decimal floating point".

> A testcase is added for the new built-in definitions.
> 
> gcc/ChangeLog:
>       * config/rs6000/dfp.md: New UNSPECDQUAN.
>       (dfp_quan_<mode>, dfp_quan_i<mode>): New define_insn.
>       * config/rs6000/rs6000-builtins.def (__builtin_dfp_quantize_64,
>       __builtin_dfp_quantize_64i, __builtin_dfp_quantize_128,
>       __builtin_dfp_quantize_128i): New buit-in definitions.
>       * config/rs6000/rs6000-overload.def (__builtin_dfp_quantize,
>       __builtin_dfpq_quantize): New overloaded definitions.
> 
> gcc/testsuite/
>        * gcc.target/powerpc/builtin-dfp-quantize-runnable.c: New test
>       case.
> ---
>  gcc/config/rs6000/dfp.md                      |  25 ++-
>  gcc/config/rs6000/rs6000-builtins.def         |  15 ++
>  gcc/config/rs6000/rs6000-overload.def         |  12 ++
>  .../powerpc/builtin-dfp-quantize-runnable.c   | 198 ++++++++++++++++++
>  4 files changed, 249 insertions(+), 1 deletion(-)
>  create mode 100644 
> gcc/testsuite/gcc.target/powerpc/builtin-dfp-quantize-runnable.c
> 
> diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
> index 5ed8a73ac51..254c22a5c20 100644
> --- a/gcc/config/rs6000/dfp.md
> +++ b/gcc/config/rs6000/dfp.md
> @@ -271,7 +271,8 @@
>     UNSPEC_DIEX
>     UNSPEC_DSCLI
>     UNSPEC_DTSTSFI
> -   UNSPEC_DSCRI])
> +   UNSPEC_DSCRI
> +   UNSPEC_DQUAN])
>  
>  (define_code_iterator DFP_TEST [eq lt gt unordered])
>  
> @@ -395,3 +396,25 @@
>    "dscri<q> %0,%1,%2"
>    [(set_attr "type" "dfp")
>     (set_attr "size" "<bits>")])
> +
> +(define_insn "dfp_quan_<mode>"

s/quan/dqua/ to aglin with the others.

> +  [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
> +        (unspec:DDTD [(match_operand:DDTD 1 "gpc_reg_operand" "d")
> +                   (match_operand:DDTD 2 "gpc_reg_operand" "d")
> +                      (match_operand:QI 3 "immediate_operand" "i")]
> +                     UNSPEC_DQUAN))]
> +  "TARGET_DFP"
> +  "dqua<q> %0,%1,%2,%3"
> +  [(set_attr "type" "dfp")
> +   (set_attr "size" "<bits>")])
> +
> +(define_insn "dfp_quan_i<mode>"

also s/quan_i/dquai_/

> +  [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
> +        (unspec:DDTD [(match_operand:SI 1 "const_int_operand" "n")
> +                   (match_operand:DDTD 2 "gpc_reg_operand" "d")
> +                      (match_operand:SI 3 "immediate_operand" "i")]
> +                     UNSPEC_DQUAN))]
> +  "TARGET_DFP"
> +  "dquai<q> %1,%0,%2,%3"
> +  [(set_attr "type" "dfp")
> +   (set_attr "size" "<bits>")])
> diff --git a/gcc/config/rs6000/rs6000-builtins.def 
> b/gcc/config/rs6000/rs6000-builtins.def
> index 35c4cdf74c5..36a56311643 100644
> --- a/gcc/config/rs6000/rs6000-builtins.def
> +++ b/gcc/config/rs6000/rs6000-builtins.def
> @@ -2983,6 +2983,21 @@
>    const unsigned long long __builtin_unpack_dec128 (_Decimal128, const 
> int<1>);
>      UNPACK_TD unpacktd {}
>  
> +  const _Decimal64 __builtin_dfp_quantize_64 (_Decimal64, _Decimal64, \
> +                                           const int<2>);
> +    DFPQUAN_64 dfp_quan_dd {}

Update with builtin_dfp_dqua and dfp_dqua_dd accordingly, similar for the below 
ones.

> +
> +  const _Decimal64 __builtin_dfp_quantize_64i (const int<5>, _Decimal64, \
> +                                              const int<2>);
> +    DFPQUAN_64i dfp_quan_idd {}
> +
> +  const _Decimal128 __builtin_dfp_quantize_128 (_Decimal128, _Decimal128, \
> +                                               const int<2>);
> +    DFPQUAN_128 dfp_quan_td {}
> +
> +  const _Decimal128 __builtin_dfp_quantize_128i (const int<5>, _Decimal128, \
> +                                                const int<2>);
> +    DFPQUAN_128i dfp_quan_itd {}
>  
>  [crypto]
>    const vull __builtin_crypto_vcipher (vull, vull);
> diff --git a/gcc/config/rs6000/rs6000-overload.def 
> b/gcc/config/rs6000/rs6000-overload.def
> index b83946f5ad8..3bb1bedd69d 100644
> --- a/gcc/config/rs6000/rs6000-overload.def
> +++ b/gcc/config/rs6000/rs6000-overload.def
> @@ -195,6 +195,18 @@
>    unsigned long long __builtin_cmpb (unsigned long long, unsigned long long);
>      CMPB
>  
> +[DFPQUAN_64, dfp_quan_64, __builtin_dfp_quantize]
> +  _Decimal64 __builtin_dfp_quantize (_Decimal64, _Decimal64, const int);
> +    DFPQUAN_64
> +  _Decimal64 __builtin_dfp_quantize (const int, _Decimal64, const int);
> +    DFPQUAN_64i
> +
> +[DFPQUAN_128, dfp_quan_128, __builtin_dfpq_quantize]
> +  _Decimal128 __builtin_dfpq_quantize (_Decimal128, _Decimal128, const int);
> +    DFPQUAN_128
> +  _Decimal128 __builtin_dfpq_quantize (const int, _Decimal128, const int);
> +    DFPQUAN_128i
> +
>  [VEC_ABS, vec_abs, __builtin_vec_abs]
>    vsc __builtin_vec_abs (vsc);
>      ABS_V16QI
> diff --git a/gcc/testsuite/gcc.target/powerpc/builtin-dfp-quantize-runnable.c 
> b/gcc/testsuite/gcc.target/powerpc/builtin-dfp-quantize-runnable.c
> new file mode 100644
> index 00000000000..f4ba7236fe3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/builtin-dfp-quantize-runnable.c

Nit: Since there is PR93448, use its name as test case name?

Also add one line as PR marker in commit log.

> @@ -0,0 +1,198 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target  dfp } */> +/* { dg-options "-O2 
> -save-temps" } */

Since this is for run, I think what you want are:

/* { dg-require-effective-target dfp_hw } */
/* { dg-require-effective-target has_arch_pwr6 } */
/* { dg-options "-mhard-float -O2 -save-temps" } */

> +
> +
> +#define DEBUG 0
> +
> +#ifdef DEBUG
> +#include <stdio.h>
> +#endif
> +#include <float.h>
> +
> +void abort (void);
> +
> +int main()
> +{
> +#define IMM2  2
> +#define IMM3  3
> +#define IMM4  4
> +
> +  _Decimal64 srcA_dfp64, srcB_dfp64;
> +  _Decimal64 result_dfp64;
> +  _Decimal64 expected_result_dfp64;
> +  _Decimal128 srcA_dfp128, srcB_dfp128;
> +  _Decimal128 result_dfp128;
> +  _Decimal128 expected_result_dfp128;
> +
> +  /* Third argument of quantize built-ins is the rounding mode value (RMC).
> +     
> +     RMC    Rounding Mode
> +     00     Round toward 0
> +     01     Round to -infinity
> +     10     Round to nearest, ties toward 0
> +     11     Round according to DRN      */

As ISA doc, the description should be:

Primary
RMC Rounding Mode
00 Round to nearest, ties to even
01 Round toward 0
10 Round to nearest, ties away from 0
11 Round according to DRN

BR,
Kewen

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