Committed, thanks Kito. Pan
From: Kito Cheng <kito.ch...@sifive.com> Sent: Wednesday, August 16, 2023 3:38 PM To: Li, Pan2 <pan2...@intel.com> Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang <yanzhang.w...@intel.com> Subject: Re: [PATCH v2] RISC-V: Support RVV VFWCVT.X.F.V rounding mode intrinsic API lgtm On Wed, Aug 16, 2023 at 3:32 PM <pan2...@intel.com<mailto:pan2...@intel.com>> wrote: From: Pan Li <pan2...@intel.com<mailto:pan2...@intel.com>> This patch would like to support the rounding mode API for the VFWCVT.X.F.V as the below samples. * __riscv_vfwcvt_x_f_v_i64m2_rm * __riscv_vfwcvt_x_f_v_i64m2_rm_m Signed-off-by: Pan Li <pan2...@intel.com<mailto:pan2...@intel.com>> gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (BASE): New declaration. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vfwcvt_x_frm): New intrinsic function def. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-wcvt-x.c: New test. --- .../riscv/riscv-vector-builtins-bases.cc | 9 +++++- .../riscv/riscv-vector-builtins-bases.h | 1 + .../riscv/riscv-vector-builtins-functions.def | 2 ++ .../riscv/rvv/base/float-point-wcvt-x.c | 29 +++++++++++++++++++ 4 files changed, 40 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-x.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index c78fa8e5b62..22640745398 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -1715,10 +1715,15 @@ public: }; /* Implements vfwcvt.x. */ -template<int UNSPEC> +template<int UNSPEC, enum frm_op_type FRM_OP = NO_FRM> class vfwcvt_x : public function_base { public: + bool has_rounding_mode_operand_p () const override + { + return FRM_OP == HAS_FRM; + } + rtx expand (function_expander &e) const override { return e.use_exact_insn ( @@ -2490,6 +2495,7 @@ static CONSTEXPR const vfcvt_rtz_x<UNSIGNED_FIX> vfcvt_rtz_xu_obj; static CONSTEXPR const vfcvt_f vfcvt_f_obj; static CONSTEXPR const vfcvt_f<HAS_FRM> vfcvt_f_frm_obj; static CONSTEXPR const vfwcvt_x<UNSPEC_VFCVT> vfwcvt_x_obj; +static CONSTEXPR const vfwcvt_x<UNSPEC_VFCVT, HAS_FRM> vfwcvt_x_frm_obj; static CONSTEXPR const vfwcvt_x<UNSPEC_UNSIGNED_VFCVT> vfwcvt_xu_obj; static CONSTEXPR const vfwcvt_rtz_x<FIX> vfwcvt_rtz_x_obj; static CONSTEXPR const vfwcvt_rtz_x<UNSIGNED_FIX> vfwcvt_rtz_xu_obj; @@ -2742,6 +2748,7 @@ BASE (vfcvt_rtz_xu) BASE (vfcvt_f) BASE (vfcvt_f_frm) BASE (vfwcvt_x) +BASE (vfwcvt_x_frm) BASE (vfwcvt_xu) BASE (vfwcvt_rtz_x) BASE (vfwcvt_rtz_xu) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index 08452587180..dd711846cbe 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -213,6 +213,7 @@ extern const function_base *const vfcvt_rtz_xu; extern const function_base *const vfcvt_f; extern const function_base *const vfcvt_f_frm; extern const function_base *const vfwcvt_x; +extern const function_base *const vfwcvt_x_frm; extern const function_base *const vfwcvt_xu; extern const function_base *const vfwcvt_rtz_x; extern const function_base *const vfwcvt_rtz_xu; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index 8dbcd946d11..4e6cc793447 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -459,6 +459,8 @@ DEF_RVV_FUNCTION (vfwcvt_f, alu, full_preds, i_to_wf_x_v_ops) DEF_RVV_FUNCTION (vfwcvt_f, alu, full_preds, u_to_wf_xu_v_ops) DEF_RVV_FUNCTION (vfwcvt_f, alu, full_preds, f_to_wf_f_v_ops) +DEF_RVV_FUNCTION (vfwcvt_x_frm, alu_frm, full_preds, f_to_wi_f_v_ops) + // 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions DEF_RVV_FUNCTION (vfncvt_x, narrow_alu, full_preds, f_to_ni_f_w_ops) DEF_RVV_FUNCTION (vfncvt_xu, narrow_alu, full_preds, f_to_nu_f_w_ops) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-x.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-x.c new file mode 100644 index 00000000000..8f67ec00966 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-x.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +vint64m2_t +test_riscv_vfwcvt_x_f_v_i64m2_rm (vfloat32m1_t op1, size_t vl) { + return __riscv_vfwcvt_x_f_v_i64m2_rm (op1, 0, vl); +} + +vint64m2_t +test_vfwcvt_x_f_v_i64m2_rm_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) { + return __riscv_vfwcvt_x_f_v_i64m2_rm_m (mask, op1, 1, vl); +} + +vint64m2_t +test_riscv_vfwcvt_x_f_v_i64m2 (vfloat32m1_t op1, size_t vl) { + return __riscv_vfwcvt_x_f_v_i64m2 (op1, vl); +} + +vint64m2_t +test_vfwcvt_x_f_v_i64m2_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) { + return __riscv_vfwcvt_x_f_v_i64m2_m (mask, op1, vl); +} + +/* { dg-final { scan-assembler-times {vfwcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */ -- 2.34.1
