[PATCH v2] RISCV: Add rotate immediate regression test

[Patrick O'Neill]

This adds new regression tests to ensure half-register rotations are
correctly optimized into rori instructions.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/zbb-rol-ror-08.c: New test.
        * gcc.target/riscv/zbb-rol-ror-09.c: New test.

Co-authored-by: Charlie Jenkins <char...@rivosinc.com>
Signed-off-by: Patrick O'Neill <patr...@rivosinc.com>
---
Trunk optimized these added testcases correctly.
GCC 13.2 and earlier do not optimize these cases correctly.

Expands on testcases added in:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;f=gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c;h=0ccf520d349a82dafca0deb3d307a1080e8589a0
---
V2 Changes:
Move testcases to new files.
---
 .../gcc.target/riscv/zbb-rol-ror-08.c         | 25 +++++++++++++++++++
 .../gcc.target/riscv/zbb-rol-ror-09.c         | 15 +++++++++++
 2 files changed, 40 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c

diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c 
b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c
new file mode 100644
index 00000000000..30696f3bb32
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-g" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-final { scan-assembler-not "and" } } */
+
+/*
+**foo1:
+**     rori    a0,a0,32
+**     ret
+*/
+unsigned long foo1(unsigned long rotate)
+{
+    return (rotate << 32) | (rotate >> 32);
+}
+
+/*
+**foo2:
+**     roriw   a0,a0,16
+**     ret
+*/
+unsigned int foo2(unsigned int rotate)
+{
+    return (rotate << 16) | (rotate >> 16);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c 
b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c
new file mode 100644
index 00000000000..a3054553e18
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -fno-lto -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-g" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-final { scan-assembler-not "and" } } */
+
+/*
+**foo1:
+**     rori    a0,a0,16
+**     ret
+*/
+unsigned int foo1(unsigned int rs1)
+{
+    return (rs1 << 16) | (rs1 >> 16);
+}
-- 
2.34.1