LGTM.
Thanks for fixing my previous mistakes.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-08-17 19:43
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw
Subject: [PATCH] RISC-V: Fix XPASS slp testcases
This patch fixs XPASS slp testcases on trunk by
making the conditions for xfail stricter.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/partial/slp-1.c: Fix.
* gcc.target/riscv/rvv/autovec/partial/slp-16.c: Ditto.
* gcc.target/riscv/rvv/autovec/partial/slp-17.c: Ditto.
* gcc.target/riscv/rvv/autovec/partial/slp-18.c: Ditto.
* gcc.target/riscv/rvv/autovec/partial/slp-19.c: Ditto.
* gcc.target/riscv/rvv/autovec/partial/slp-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/partial/slp-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/partial/slp-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/partial/slp-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/partial/slp-6.c: Ditto.
---
.../gcc.target/riscv/rvv/autovec/partial/slp-1.c | 9 +++++----
.../gcc.target/riscv/rvv/autovec/partial/slp-16.c | 7 ++++---
.../gcc.target/riscv/rvv/autovec/partial/slp-17.c | 7 ++++---
.../gcc.target/riscv/rvv/autovec/partial/slp-18.c | 7 ++++---
.../gcc.target/riscv/rvv/autovec/partial/slp-19.c | 6 ++++--
.../gcc.target/riscv/rvv/autovec/partial/slp-2.c | 5 +++--
.../gcc.target/riscv/rvv/autovec/partial/slp-3.c | 5 +++--
.../gcc.target/riscv/rvv/autovec/partial/slp-4.c | 5 +++--
.../gcc.target/riscv/rvv/autovec/partial/slp-5.c | 5 +++--
.../gcc.target/riscv/rvv/autovec/partial/slp-6.c | 5 +++--
10 files changed, 36 insertions(+), 25 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c
index 788e0450b47..3571a325f73 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c
@@ -19,7 +19,8 @@ f (int8_t *restrict a, int8_t *restrict b, int n)
}
}
-/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are
chosen instead of SLP. */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail *-*-*
} } } */
-/* { dg-final { scan-assembler {\tvid\.v} { xfail *-*-* } } } */
-/* { dg-final { scan-assembler {\tvand} { xfail *-*-* } } } */
+/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are
chosen
+ instead of SLP when riscv-autovec-lmul=m1 or m2. */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail {
any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } }
} */
+/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param
riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */
+/* { dg-final { scan-assembler {\tvand} { xfail { any-opts "--param
riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c
index b58e270eaa4..8c5c65152c8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c
@@ -19,7 +19,8 @@ f (uint8_t *restrict a, uint8_t *restrict b, int n)
}
}
-/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are
chosen instead of SLP. */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail *-*-*
} } } */
-/* { dg-final { scan-assembler {\tvid\.v} { xfail *-*-* } } } */
+/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are
chosen
+ instead of SLP when riscv-autovec-lmul=m1 or m2. */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail {
any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } }
} */
+/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param
riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */
/* { dg-final { scan-assembler-not {\tvmul} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c
index bccf3e6570a..67dbadafc48 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c
@@ -29,7 +29,8 @@ f (uint8_t *restrict a, uint8_t *restrict b,
}
}
-/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are
chosen instead of SLP. */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 2 "optimized" { xfail *-*-*
} } } */
-/* { dg-final { scan-assembler {\tvid\.v} { xfail *-*-* } } } */
+/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are
chosen
+ instead of SLP when riscv-autovec-lmul=m1. */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 2 "optimized" { xfail {
any-opts "--param riscv-autovec-lmul=m1" } } } } */
+/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param
riscv-autovec-lmul=m1" } } } } */
/* { dg-final { scan-assembler-not {\tvmul} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c
index f00bece1414..6e60dabb85f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c
@@ -21,7 +21,8 @@ f (float *restrict a, float *restrict b,
}
}
-/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are
chosen instead of SLP. */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail *-*-*
} } } */
-/* { dg-final { scan-assembler {\tvid\.v} { xfail *-*-* } } } */
+/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are
chosen
+ instead of SLP when riscv-autovec-lmul=m1 or m2. */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 2 "optimized" { xfail {
any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } }
} */
+/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param
riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */
/* { dg-final { scan-assembler-not {\tvmul} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c
index 67db75517c3..309c30e4735 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c
@@ -21,6 +21,8 @@ f (float *restrict a, float *restrict b,
}
}
-/* { dg-final { scan-tree-dump "\.VEC_PERM" "optimized" { xfail *-*-* } } } */
-/* { dg-final { scan-assembler {\tvid\.v} { xfail *-*-* } } } */
+/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are
chosen
+ instead of SLP when riscv-autovec-lmul=m1 or m2. */
+/* { dg-final { scan-tree-dump "\.VEC_PERM" "optimized" { xfail { any-opts
"--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */
+/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param
riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */
/* { dg-final { scan-assembler-not {\tvmul} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c
index ad60b11d815..5605b1ba684 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c
@@ -19,5 +19,6 @@ f (int16_t *restrict a, int16_t *restrict b, int n)
}
}
-/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are
chosen instead of SLP. */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail *-*-*
} } } */
+/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are
chosen
+ instead of SLP when riscv-autovec-lmul=m1. */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail {
any-opts "--param riscv-autovec-lmul=m1" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c
index 088828f326f..fde54e1f059 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c
@@ -19,5 +19,6 @@ f (int8_t *restrict a, int8_t *restrict b, int n)
}
}
-/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are
chosen instead of SLP. */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail *-*-*
} } } */
+/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are
chosen
+ instead of SLP when riscv-autovec-lmul=m1 or m2. */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail {
any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } }
} */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c
index d56feeb8fdf..e18ebd3ae2f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c
@@ -19,5 +19,6 @@ f (int16_t *restrict a, int16_t *restrict b, int n)
}
}
-/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are
chosen instead of SLP. */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail *-*-*
} } } */
+/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are
chosen
+ instead of SLP when riscv-autovec-lmul=m1. */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail {
any-opts "--param riscv-autovec-lmul=m1" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c
index d825a257ccd..600699be9d1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c
@@ -19,5 +19,6 @@ f (int8_t *restrict a, int8_t *restrict b, int n)
}
}
-/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are
chosen instead of SLP. */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail *-*-*
} } } */
+/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are
chosen
+ instead of SLP when riscv-autovec-lmul=m1 or m2. */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail {
any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } }
} */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c
index 160880c42b7..9fca6bdf5d0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c
@@ -19,6 +19,7 @@ f (uint8_t *restrict a, uint8_t *restrict b, int n)
}
}
-/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are
chosen instead of SLP. */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail *-*-*
} } } */
+/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are
chosen
+ instead of SLP when riscv-autovec-lmul=m1. */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail {
any-opts "--param riscv-autovec-lmul=m1" } } } } */
--
2.36.3
