Hi,
This patch add conditional FP extendsion and truncation autovec
patterns. This patch depend on other patch
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628235.html .
Best,
Lehua
gcc/ChangeLog:
* config/riscv/autovec-opt.md (*cond_extend<v_double_trunc><mode>):
Add combine pattern.
(*cond_trunc<mode><v_double_trunc>): Ditto.
* config/riscv/autovec.md: Adjust for combine.
* config/riscv/riscv-protos.h (emit_vlmax_masked_fp_insn): Exported.
* config/riscv/riscv-v.cc (emit_vlmax_masked_fp_insn): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-1.h: New
test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-2.h: New
test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c:
New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c:
New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c:
New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c:
New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c:
New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c:
New test.
---
gcc/config/riscv/autovec-opt.md | 35 +++++++++++++++++++
gcc/config/riscv/autovec.md | 15 +++-----
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-v.cc | 19 ++++++++++
.../autovec/cond/cond_convert_float2float-1.h | 30 ++++++++++++++++
.../autovec/cond/cond_convert_float2float-2.h | 28 +++++++++++++++
.../cond/cond_convert_float2float-rv32-1.c | 9 +++++
.../cond/cond_convert_float2float-rv32-2.c | 9 +++++
.../cond/cond_convert_float2float-rv64-1.c | 9 +++++
.../cond/cond_convert_float2float-rv64-2.c | 9 +++++
.../cond/cond_convert_float2float_run-1.c | 31 ++++++++++++++++
.../cond/cond_convert_float2float_run-2.c | 30 ++++++++++++++++
12 files changed, 214 insertions(+), 11 deletions(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-1.h
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-2.h
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index f3ef3a839df..8f9a6317592 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -792,3 +792,38 @@
riscv_vector::emit_vlmax_masked_insn (icode, riscv_vector::RVV_UNOP_M,
operands);
DONE;
})
+
+;; Combine FP sign_extend/zero_extend(vf2) and vcond_mask
+(define_insn_and_split "*cond_extend<v_double_trunc><mode>"
+ [(set (match_operand:VWEXTF_ZVFHMIN 0 "register_operand")
+ (if_then_else:VWEXTF_ZVFHMIN
+ (match_operand:<VM> 1 "register_operand")
+ (float_extend:VWEXTF_ZVFHMIN (match_operand:<V_DOUBLE_TRUNC> 3
"register_operand"))
+ (match_operand:VWEXTF_ZVFHMIN 2 "register_operand")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ insn_code icode = code_for_pred_extend (<MODE>mode);
+ riscv_vector::emit_vlmax_masked_insn (icode, riscv_vector::RVV_UNOP_M,
operands);
+ DONE;
+})
+
+;; Combine FP trunc(vf2) + vcond_mask
+(define_insn_and_split "*cond_trunc<mode><v_double_trunc>"
+ [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand")
+ (if_then_else:<V_DOUBLE_TRUNC>
+ (match_operand:<VM> 1 "register_operand")
+ (float_truncate:<V_DOUBLE_TRUNC>
+ (match_operand:VWEXTF_ZVFHMIN 3 "register_operand"))
+ (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ insn_code icode = code_for_pred_trunc (<MODE>mode);
+ riscv_vector::emit_vlmax_masked_fp_insn (icode, riscv_vector::RVV_UNOP_M,
operands);
+ DONE;
+})
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 4936333f303..f2bf5e045ee 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -752,14 +752,9 @@
(match_operand:<V_QUAD_TRUNC> 1 "register_operand")))]
"TARGET_VECTOR && (TARGET_ZVFHMIN || TARGET_ZVFH)"
{
- rtx dblw = gen_reg_rtx (<V_DOUBLE_TRUNC>mode);
- insn_code icode = code_for_pred_extend (<V_DOUBLE_TRUNC>mode);
- rtx ops1[] = {dblw, operands[1]};
- riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, ops1);
-
- icode = code_for_pred_extend (<MODE>mode);
- rtx ops2[] = {operands[0], dblw};
- riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, ops2);
+ rtx half = gen_reg_rtx (<V_DOUBLE_TRUNC>mode);
+ emit_insn (gen_extend<v_quad_trunc><v_double_trunc>2 (half, operands[1]));
+ emit_insn (gen_extend<v_double_trunc><mode>2 (operands[0], half));
DONE;
})
@@ -802,9 +797,7 @@
insn_code icode = code_for_pred_rod_trunc (<MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, opshalf);
- rtx ops[] = {operands[0], half};
- icode = code_for_pred_trunc (<V_DOUBLE_TRUNC>mode);
- riscv_vector::emit_vlmax_fp_insn (icode, riscv_vector::RVV_UNOP, ops);
+ emit_insn (gen_trunc<v_double_trunc><v_quad_trunc>2 (operands[0], half));
DONE;
})
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 558330718a1..ecd9d22ba25 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -256,6 +256,7 @@ void emit_vlmax_cmp_insn (unsigned, rtx *);
void emit_vlmax_cmp_mu_insn (unsigned, rtx *);
void emit_vlmax_masked_insn (unsigned, int, rtx *);
void emit_vlmax_masked_mu_insn (unsigned, int, rtx *);
+void emit_vlmax_masked_fp_insn (unsigned, int, rtx *);
void emit_scalar_move_insn (unsigned, rtx *, rtx = 0);
void emit_nonvlmax_integer_move_insn (unsigned, rtx *, rtx);
enum vlmul_type get_vlmul (machine_mode);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index a2cf006804b..887ce367600 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -922,6 +922,25 @@ emit_vlmax_masked_insn (unsigned icode, int op_num, rtx
*ops)
e.emit_insn ((enum insn_code) icode, ops);
}
+/* This function emits a masked instruction which depend FRM_DYN. */
+void
+emit_vlmax_masked_fp_insn (unsigned icode, int op_num, rtx *ops)
+{
+ machine_mode dest_mode = GET_MODE (ops[0]);
+ machine_mode mask_mode = get_mask_mode (dest_mode);
+ insn_expander<RVV_INSN_OPERANDS_MAX> e (/*OP_NUM*/ op_num,
+ /*HAS_DEST_P*/ true,
+ /*FULLY_UNMASKED_P*/ false,
+ /*USE_REAL_MERGE_P*/ true,
+ /*HAS_AVL_P*/ true,
+ /*VLMAX_P*/ true, dest_mode,
+ mask_mode);
+ e.set_policy (TAIL_ANY);
+ e.set_policy (MASK_ANY);
+ e.set_rounding_mode (FRM_DYN);
+ e.emit_insn ((enum insn_code) icode, ops);
+}
+
/* This function emits a masked instruction. */
static void
emit_nonvlmax_masked_insn (unsigned icode, int op_num, rtx *ops, rtx avl)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-1.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-1.h
new file mode 100644
index 00000000000..1b72069c884
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-1.h
@@ -0,0 +1,30 @@
+#include <stdint.h>
+
+#define DEF_LOOP(OLD_TYPE, NEW_TYPE)
\
+ void __attribute__ ((noipa))
\
+ test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r,
\
+ OLD_TYPE *__restrict a, \
+ NEW_TYPE *__restrict b, \
+ OLD_TYPE *__restrict pred, int n) \
+ {
\
+ for (int i = 0; i < n; ++i)
\
+ {
\
+ NEW_TYPE bi = b[i]; \
+ r[i] = pred[i] ? (NEW_TYPE) a[i] : bi; \
+ }
\
+ }
+
+/* wider-width Float Type => Float Type */
+#define TEST_ALL_F2F_WIDER(T)
\
+ T (_Float16, float)
\
+ T (_Float16, double)
\
+ T (float, double)
+
+/* narrower-width Float Type => Float Type */
+#define TEST_ALL_F2F_NARROWER(T)
\
+ T (float, _Float16)
\
+ T (double, _Float16)
\
+ T (double, float)
+
+TEST_ALL_F2F_WIDER (DEF_LOOP)
+TEST_ALL_F2F_NARROWER (DEF_LOOP)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-2.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-2.h
new file mode 100644
index 00000000000..41597417a84
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-2.h
@@ -0,0 +1,28 @@
+#include <stdint.h>
+
+#define DEF_LOOP(OLD_TYPE, NEW_TYPE)
\
+ void __attribute__ ((noipa))
\
+ test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r,
\
+ OLD_TYPE *__restrict a, NEW_TYPE b, \
+ OLD_TYPE *__restrict pred, int n) \
+ {
\
+ for (int i = 0; i < n; ++i)
\
+ {
\
+ r[i] = pred[i] ? (NEW_TYPE) a[i] : b; \
+ }
\
+ }
+
+/* wider-width Float Type => Float Type */
+#define TEST_ALL_F2F_WIDER(T)
\
+ T (_Float16, float)
\
+ T (_Float16, double)
\
+ T (float, double)
+
+/* narrower-width Float Type => Float Type */
+#define TEST_ALL_F2F_NARROWER(T)
\
+ T (float, _Float16)
\
+ T (double, _Float16)
\
+ T (double, float)
+
+TEST_ALL_F2F_WIDER (DEF_LOOP)
+TEST_ALL_F2F_NARROWER (DEF_LOOP)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c
new file mode 100644
index 00000000000..e0d9eaa4173
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param
riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+
+#include "cond_convert_float2float-1.h"
+
+/* { dg-final { scan-assembler-times
{\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+\n} 1
} } */
+/* { dg-final { scan-assembler-times
{\tvfncvt\.f\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times
{\tvfncvt\.rod\.f\.f\.w\tv[0-9]+,v[0-9]+\n} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c
new file mode 100644
index 00000000000..8d963b0397b
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param
riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+
+#include "cond_convert_float2float-2.h"
+
+/* { dg-final { scan-assembler-times
{\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+\n} 1
} } */
+/* { dg-final { scan-assembler-times
{\tvfncvt\.f\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times
{\tvfncvt\.rod\.f\.f\.w\tv[0-9]+,v[0-9]+\n} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c
new file mode 100644
index 00000000000..9841fdd7f79
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param
riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+
+#include "cond_convert_float2float-1.h"
+
+/* { dg-final { scan-assembler-times
{\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+\n} 1
} } */
+/* { dg-final { scan-assembler-times
{\tvfncvt\.f\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times
{\tvfncvt\.rod\.f\.f\.w\tv[0-9]+,v[0-9]+\n} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c
new file mode 100644
index 00000000000..03ee19fa9e8
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param
riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+
+#include "cond_convert_float2float-2.h"
+
+/* { dg-final { scan-assembler-times
{\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+\n} 1
} } */
+/* { dg-final { scan-assembler-times
{\tvfncvt\.f\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times
{\tvfncvt\.rod\.f\.f\.w\tv[0-9]+,v[0-9]+\n} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c
new file mode 100644
index 00000000000..407bbc27c2f
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c
@@ -0,0 +1,31 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable
-fno-vect-cost-model -ffast-math" } */
+
+#include "cond_convert_float2float-1.h"
+
+#define N 99
+
+#define TEST_LOOP(OLD_TYPE, NEW_TYPE)
\
+ {
\
+ NEW_TYPE r[N], b[N];
\
+ OLD_TYPE a[N], pred[N];
\
+ for (int i = 0; i < N; ++i)
\
+ {
\
+ a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \
+ b[i] = (i % 9) * (i % 7 + 1); \
+ pred[i] = (i % 7 < 4); \
+ asm volatile("" ::: "memory"); \
+ }
\
+ test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N);
\
+ for (int i = 0; i < N; ++i)
\
+ if (r[i] != (pred[i] ? (NEW_TYPE) a[i] : b[i]))
\
+ __builtin_abort (); \
+ }
+
+int
+main ()
+{
+ TEST_ALL_F2F_WIDER (TEST_LOOP)
+ TEST_ALL_F2F_NARROWER (TEST_LOOP)
+ return 0;
+}
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c
new file mode 100644
index 00000000000..05d217da625
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c
@@ -0,0 +1,30 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable
-fno-vect-cost-model -ffast-math" } */
+
+#include "cond_convert_float2float-2.h"
+
+#define N 99
+
+#define TEST_LOOP(OLD_TYPE, NEW_TYPE)
\
+ {
\
+ NEW_TYPE r[N], b = 18.02;
\
+ OLD_TYPE a[N], pred[N];
\
+ for (int i = 0; i < N; ++i)
\
+ {
\
+ a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \
+ pred[i] = (i % 7 < 4); \
+ asm volatile("" ::: "memory"); \
+ }
\
+ test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N);
\
+ for (int i = 0; i < N; ++i)
\
+ if (r[i] != (pred[i] ? (NEW_TYPE) a[i] : b))
\
+ __builtin_abort (); \
+ }
+
+int
+main ()
+{
+ TEST_ALL_F2F_WIDER (TEST_LOOP)
+ TEST_ALL_F2F_NARROWER (TEST_LOOP)
+ return 0;
+}
--
2.36.3
