Richard Earnshaw via Gcc-patches <gcc-patches@gcc.gnu.org> writes:
> Note, this patch is dependent on the patch I posted yesterday to
> forward declare rtx_code in coretypes.h.
>
> ------
> Now that we have a forward declaration of rtx_code in coretypes.h, we
> can adjust these hooks to take rtx_code arguments rather than an int.
>
> gcc/ChangeLog:
>
> * target.def (gen_ccmp_first, gen_ccmp_next): Use rtx_code for
> CODE, CMP_CODE and BIT_CODE arguments.
> * config/aarch64/aarch64.cc (aarch64_gen_ccmp_first): Likewise.
> (aarch64_gen_ccmp_next): Likewise.
> * doc/tm.texi: Regenerated.
OK, thanks.
Richard
> ---
> gcc/config/aarch64/aarch64.cc | 5 +++--
> gcc/doc/tm.texi | 4 ++--
> gcc/target.def | 4 ++--
> 3 files changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
> index 560e5431636..bc09185b8ec 100644
> --- a/gcc/config/aarch64/aarch64.cc
> +++ b/gcc/config/aarch64/aarch64.cc
> @@ -25585,7 +25585,7 @@ aarch64_asan_shadow_offset (void)
>
> static rtx
> aarch64_gen_ccmp_first (rtx_insn **prep_seq, rtx_insn **gen_seq,
> - int code, tree treeop0, tree treeop1)
> + rtx_code code, tree treeop0, tree treeop1)
> {
> machine_mode op_mode, cmp_mode, cc_mode = CCmode;
> rtx op0, op1;
> @@ -25659,7 +25659,8 @@ aarch64_gen_ccmp_first (rtx_insn **prep_seq, rtx_insn
> **gen_seq,
>
> static rtx
> aarch64_gen_ccmp_next (rtx_insn **prep_seq, rtx_insn **gen_seq, rtx prev,
> - int cmp_code, tree treeop0, tree treeop1, int bit_code)
> + rtx_code cmp_code, tree treeop0, tree treeop1,
> + rtx_code bit_code)
> {
> rtx op0, op1, target;
> machine_mode op_mode, cmp_mode, cc_mode = CCmode;
> diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
> index 95ba56e05ae..75cb8e3417c 100644
> --- a/gcc/doc/tm.texi
> +++ b/gcc/doc/tm.texi
> @@ -12005,7 +12005,7 @@ This target hook is required only when the target has
> several different
> modes and they have different conditional execution capability, such as ARM.
> @end deftypefn
>
> -@deftypefn {Target Hook} rtx TARGET_GEN_CCMP_FIRST (rtx_insn
> **@var{prep_seq}, rtx_insn **@var{gen_seq}, int @var{code}, tree @var{op0},
> tree @var{op1})
> +@deftypefn {Target Hook} rtx TARGET_GEN_CCMP_FIRST (rtx_insn
> **@var{prep_seq}, rtx_insn **@var{gen_seq}, rtx_code @var{code}, tree
> @var{op0}, tree @var{op1})
> This function prepares to emit a comparison insn for the first compare in a
> sequence of conditional comparisions. It returns an appropriate comparison
> with @code{CC} for passing to @code{gen_ccmp_next} or @code{cbranch_optab}.
> @@ -12015,7 +12015,7 @@ This function prepares to emit a comparison insn for
> the first compare in a
> @var{code} is the @code{rtx_code} of the compare for @var{op0} and
> @var{op1}.
> @end deftypefn
>
> -@deftypefn {Target Hook} rtx TARGET_GEN_CCMP_NEXT (rtx_insn
> **@var{prep_seq}, rtx_insn **@var{gen_seq}, rtx @var{prev}, int
> @var{cmp_code}, tree @var{op0}, tree @var{op1}, int @var{bit_code})
> +@deftypefn {Target Hook} rtx TARGET_GEN_CCMP_NEXT (rtx_insn
> **@var{prep_seq}, rtx_insn **@var{gen_seq}, rtx @var{prev}, rtx_code
> @var{cmp_code}, tree @var{op0}, tree @var{op1}, rtx_code @var{bit_code})
> This function prepares to emit a conditional comparison within a sequence
> of conditional comparisons. It returns an appropriate comparison with
> @code{CC} for passing to @code{gen_ccmp_next} or @code{cbranch_optab}.
> diff --git a/gcc/target.def b/gcc/target.def
> index 7d684296c17..3ad0bde3ece 100644
> --- a/gcc/target.def
> +++ b/gcc/target.def
> @@ -2735,7 +2735,7 @@ DEFHOOK
> insns are saved in @var{gen_seq}. They will be emitted when all the\n\
> compares in the conditional comparision are generated without error.\n\
> @var{code} is the @code{rtx_code} of the compare for @var{op0} and
> @var{op1}.",
> - rtx, (rtx_insn **prep_seq, rtx_insn **gen_seq, int code, tree op0, tree
> op1),
> + rtx, (rtx_insn **prep_seq, rtx_insn **gen_seq, rtx_code code, tree op0,
> tree op1),
> NULL)
>
> DEFHOOK
> @@ -2752,7 +2752,7 @@ DEFHOOK
> be appropriate for passing to @code{gen_ccmp_next} or
> @code{cbranch_optab}.\n\
> @var{code} is the @code{rtx_code} of the compare for @var{op0} and
> @var{op1}.\n\
> @var{bit_code} is @code{AND} or @code{IOR}, which is the op on the
> compares.",
> - rtx, (rtx_insn **prep_seq, rtx_insn **gen_seq, rtx prev, int cmp_code, tree
> op0, tree op1, int bit_code),
> + rtx, (rtx_insn **prep_seq, rtx_insn **gen_seq, rtx prev, rtx_code cmp_code,
> tree op0, tree op1, rtx_code bit_code),
> NULL)
>
> /* Return a new value for loop unroll size. */
