lgtm
On Fri, Aug 25, 2023 at 9:49 AM Pan Li via Gcc-patches <gcc-patches@gcc.gnu.org> wrote: > > From: Pan Li <pan2...@intel.com> > > There will be a case like below for intrinsic and autovec combination. > > vfadd RTZ <- intrinisc static rounding > vfnmadd <- autovec/autovec-opt > > The autovec generated vfnmadd should take DYN mode, and the > frm must be restored before the vfnmadd insn. This patch > would like to fix this issue by: > > * Add the frm operand to the autovec/autovec-opt pattern. > * Set the frm_mode attr to DYN. > > Thus, the frm flow when combine autovec and intrinsic should be. > > +------------ > | frrm a5 > | ... > | fsrmi 4 > | vfadd <- intrinsic static rounding. > | ... > | fsrm a5 > | vfnmadd <- autovec/autovec-opt > | ... > +------------ > > Signed-off-by: Pan Li <pan2...@intel.com> > > gcc/ChangeLog: > > * config/riscv/autovec-opt.md: Add FRM_REGNUM to vfnmadd/vfnmacc. > * config/riscv/autovec.md: Ditto. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c: New test. > --- > gcc/config/riscv/autovec-opt.md | 38 ++++---- > gcc/config/riscv/autovec.md | 34 ++++--- > .../rvv/base/float-point-frm-autovec-4.c | 88 +++++++++++++++++++ > 3 files changed, 130 insertions(+), 30 deletions(-) > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c > > diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md > index 54ca6df721c..2922f370a17 100644 > --- a/gcc/config/riscv/autovec-opt.md > +++ b/gcc/config/riscv/autovec-opt.md > @@ -655,14 +655,16 @@ (define_insn_and_split "*single_widen_fms<mode>" > ;; vect__13.182_33 = .FNMS (vect__11.180_35, vect__8.176_40, vect__4.172_45); > (define_insn_and_split "*double_widen_fnms<mode>" > [(set (match_operand:VWEXTF 0 "register_operand") > - (fma:VWEXTF > - (neg:VWEXTF > + (unspec:VWEXTF > + [(fma:VWEXTF > + (neg:VWEXTF > + (float_extend:VWEXTF > + (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))) > (float_extend:VWEXTF > - (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))) > - (float_extend:VWEXTF > - (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand")) > - (neg:VWEXTF > - (match_operand:VWEXTF 1 "register_operand"))))] > + (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand")) > + (neg:VWEXTF > + (match_operand:VWEXTF 1 "register_operand"))) > + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))] > "TARGET_VECTOR && can_create_pseudo_p ()" > "#" > "&& 1" > @@ -673,18 +675,21 @@ (define_insn_and_split "*double_widen_fnms<mode>" > DONE; > } > [(set_attr "type" "vfwmuladd") > - (set_attr "mode" "<V_DOUBLE_TRUNC>")]) > + (set_attr "mode" "<V_DOUBLE_TRUNC>") > + (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))]) > > ;; This helps to match ext + fnms. > (define_insn_and_split "*single_widen_fnms<mode>" > [(set (match_operand:VWEXTF 0 "register_operand") > - (fma:VWEXTF > - (neg:VWEXTF > - (float_extend:VWEXTF > - (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))) > - (match_operand:VWEXTF 3 "register_operand") > - (neg:VWEXTF > - (match_operand:VWEXTF 1 "register_operand"))))] > + (unspec:VWEXTF > + [(fma:VWEXTF > + (neg:VWEXTF > + (float_extend:VWEXTF > + (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))) > + (match_operand:VWEXTF 3 "register_operand") > + (neg:VWEXTF > + (match_operand:VWEXTF 1 "register_operand"))) > + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))] > "TARGET_VECTOR && can_create_pseudo_p ()" > "#" > "&& 1" > @@ -701,4 +706,5 @@ (define_insn_and_split "*single_widen_fnms<mode>" > DONE; > } > [(set_attr "type" "vfwmuladd") > - (set_attr "mode" "<V_DOUBLE_TRUNC>")]) > + (set_attr "mode" "<V_DOUBLE_TRUNC>") > + (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))]) > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md > index 28396c6175d..5f16ac53712 100644 > --- a/gcc/config/riscv/autovec.md > +++ b/gcc/config/riscv/autovec.md > @@ -1274,26 +1274,31 @@ (define_insn_and_split "*fms<VF:mode><P:mode>" > (define_expand "fnms<mode>4" > [(parallel > [(set (match_operand:VF 0 "register_operand") > - (fma:VF > - (neg:VF > - (match_operand:VF 1 "register_operand")) > - (match_operand:VF 2 "register_operand") > - (neg:VF > - (match_operand:VF 3 "register_operand")))) > + (unspec:VF > + [(fma:VF > + (neg:VF > + (match_operand:VF 1 "register_operand")) > + (match_operand:VF 2 "register_operand") > + (neg:VF > + (match_operand:VF 3 "register_operand"))) > + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA)) > (clobber (match_dup 4))])] > "TARGET_VECTOR" > { > operands[4] = gen_reg_rtx (Pmode); > - }) > + } > + [(set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))]) > > (define_insn_and_split "*fnms<VF:mode><P:mode>" > [(set (match_operand:VF 0 "register_operand" "=vr, vr, ?&vr") > - (fma:VF > - (neg:VF > - (match_operand:VF 1 "register_operand" " %0, vr, vr")) > - (match_operand:VF 2 "register_operand" " vr, vr, vr") > - (neg:VF > - (match_operand:VF 3 "register_operand" " vr, 0, vr")))) > + (unspec:VF > + [(fma:VF > + (neg:VF > + (match_operand:VF 1 "register_operand" " %0, vr, vr")) > + (match_operand:VF 2 "register_operand" " vr, vr, vr") > + (neg:VF > + (match_operand:VF 3 "register_operand" " vr, 0, vr"))) > + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA)) > (clobber (match_operand:P 4 "register_operand" "=r,r,r"))] > "TARGET_VECTOR" > "#" > @@ -1307,7 +1312,8 @@ (define_insn_and_split "*fnms<VF:mode><P:mode>" > DONE; > } > [(set_attr "type" "vfmuladd") > - (set_attr "mode" "<VF:MODE>")]) > + (set_attr "mode" "<VF:MODE>") > + (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))]) > > ;; ========================================================================= > ;; == SELECT_VL > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c > b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c > new file mode 100644 > index 00000000000..2cc4e0ae38e > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c > @@ -0,0 +1,88 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax > -ffast-math -mabi=lp64 -O3 -Wno-psabi" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +#include "riscv_vector.h" > + > +/* > +**test_1: > +** ... > +** frrm\t[axt][0-9]+ > +** ... > +** fsrmi\t1 > +** ... > +** vfadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ > +** ... > +** fsrm\t[axt][0-9]+ > +** ... > +** vfnmadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ > +** ... > +** ret > +*/ > +void > +test_1 (vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t *op_out, size_t vl, > + double *in1, double *in2, double *out) > +{ > + *op_out = __riscv_vfadd_vv_f32m1_rm (op1, op2, 1, vl); > + > + for (int i = 0; i < vl; ++i) > + out[i] = - in1[i] * in2[i] - out[i]; > +} > + > +/* > +**test_2: > +** ... > +** frrm\t[axt][0-9]+ > +** ... > +** fsrmi\t1 > +** ... > +** vfadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ > +** ... > +** fsrm\t[axt][0-9]+ > +** ... > +** vfnmadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ > +** ... > +** fsrmi\t4 > +** ... > +** vfadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ > +** ... > +** fsrm\t[axt][0-9]+ > +** ... > +** ret > +*/ > +void > +test_2 (vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t *op_out, size_t vl, > + double *in1, double *in2, double *out) > +{ > + op2 = __riscv_vfadd_vv_f32m1_rm (op1, op2, 1, vl); > + > + for (int i = 0; i < vl; ++i) > + out[i] = - out[i] * in1[i] - in2[i]; > + > + *op_out = __riscv_vfadd_vv_f32m1_rm (op1, op2, 4, vl); > +} > + > +/* > +**test_3: > +** ... > +** frrm\t[axt][0-9]+ > +** ... > +** vfnmadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ > +** ... > +** fsrmi\t4 > +** ... > +** vfadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ > +** ... > +** fsrm\t[axt][0-9]+ > +** ... > +** ret > +*/ > +void > +test_3 (vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t *op_out, size_t vl, > + double *in1, double *in2, double *in3, double *out) > +{ > + for (int i = 0; i < vl; ++i) > + out[i] = - in2[i] * out[i] - in1[i]; > + > + *op_out = __riscv_vfadd_vv_f32m1_rm (op1, op2, 4, vl); > +} > -- > 2.34.1 >