This is a follow-up for the zfa extension, added according to the recommendations for zvfh and patch of Tsukasa OI <research_tra...@irq.a4lg.com>. At the same time, zfa-fli-5.c of which is also based on the patch.
Ref: https://gcc.gnu.org/pipermail/gcc-patches/2023-August/627284.html https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628492.html gcc/ChangeLog: * config/riscv/riscv.cc (riscv_float_const_rtx_index_for_fli): zvfh can generate zfa extended instruction fli.h, just like zfh. gcc/testsuite/ChangeLog: * gcc.target/riscv/zfa-fli-7.c: Change fa0 to fa\[0-9\] to avoid assigning register numbers that are non-zero. * gcc.target/riscv/zfa-fli-8.c: Ditto. * gcc.target/riscv/zfa-fli-5.c: New test. --- gcc/config/riscv/riscv.cc | 2 +- gcc/testsuite/gcc.target/riscv/zfa-fli-5.c | 99 ++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/zfa-fli-7.c | 6 +- gcc/testsuite/gcc.target/riscv/zfa-fli-8.c | 2 +- 4 files changed, 104 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli-5.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 1d6e278ea90..e839367c0c1 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -865,7 +865,7 @@ riscv_float_const_rtx_index_for_fli (rtx x) if (!TARGET_ZFA || !CONST_DOUBLE_P(x) || mode == VOIDmode - || (mode == HFmode && !TARGET_ZFH) + || (mode == HFmode && !(TARGET_ZFH || TARGET_ZVFH)) || (mode == SFmode && !TARGET_HARD_FLOAT) || (mode == DFmode && !TARGET_DOUBLE_FLOAT)) return -1; diff --git a/gcc/testsuite/gcc.target/riscv/zfa-fli-5.c b/gcc/testsuite/gcc.target/riscv/zfa-fli-5.c new file mode 100644 index 00000000000..f6ec8f6d99d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zfa-fli-5.c @@ -0,0 +1,99 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64imf_zfa_zvfh -mabi=lp64f" { target { rv64 } } } */ +/* { dg-options "-march=rv32imf_zfa_zvfh -mabi=ilp32f" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } {"-O0" "-Og" "-Oz"} } */ + +/* Even if 'Zfh' is disabled, "fli.h" is usable when + both 'Zfa' and 'Zvfh' are available. */ +#ifdef __riscv_zfh +#error Invalid feature macro defined +#endif + +#define TYPE_h _Float16 + +#define DECL_TYPE(TYPE_SHORT) TYPE_##TYPE_SHORT + +#define DECL_FUNC(TYPE_SHORT, N, VALUE) \ + DECL_TYPE (TYPE_SHORT) const_##TYPE_SHORT##_##N (void) \ + { \ + return VALUE; \ + } + +#define DECL_FINITE_FUNCS(TYPE_SHORT) \ + DECL_FUNC (TYPE_SHORT, 00, -1) \ + DECL_FUNC (TYPE_SHORT, 02, 0.0000152587890625) \ + DECL_FUNC (TYPE_SHORT, 03, 0.000030517578125) \ + DECL_FUNC (TYPE_SHORT, 04, 0.00390625) \ + DECL_FUNC (TYPE_SHORT, 05, 0.0078125) \ + DECL_FUNC (TYPE_SHORT, 06, 0.0625) \ + DECL_FUNC (TYPE_SHORT, 07, 0.125) \ + DECL_FUNC (TYPE_SHORT, 08, 0.25) \ + DECL_FUNC (TYPE_SHORT, 09, 0.3125) \ + DECL_FUNC (TYPE_SHORT, 10, 0.375) \ + DECL_FUNC (TYPE_SHORT, 11, 0.4375) \ + DECL_FUNC (TYPE_SHORT, 12, 0.5) \ + DECL_FUNC (TYPE_SHORT, 13, 0.625) \ + DECL_FUNC (TYPE_SHORT, 14, 0.75) \ + DECL_FUNC (TYPE_SHORT, 15, 0.875) \ + DECL_FUNC (TYPE_SHORT, 16, 1) \ + DECL_FUNC (TYPE_SHORT, 17, 1.25) \ + DECL_FUNC (TYPE_SHORT, 18, 1.5) \ + DECL_FUNC (TYPE_SHORT, 19, 1.75) \ + DECL_FUNC (TYPE_SHORT, 20, 2) \ + DECL_FUNC (TYPE_SHORT, 21, 2.5) \ + DECL_FUNC (TYPE_SHORT, 22, 3) \ + DECL_FUNC (TYPE_SHORT, 23, 4) \ + DECL_FUNC (TYPE_SHORT, 24, 8) \ + DECL_FUNC (TYPE_SHORT, 25, 16) \ + DECL_FUNC (TYPE_SHORT, 26, 128) \ + DECL_FUNC (TYPE_SHORT, 27, 256) \ + DECL_FUNC (TYPE_SHORT, 28, 32768) \ + DECL_FUNC (TYPE_SHORT, 29, 65536) + +/* Finite numbers (except 2^16 in _Float16, making an inf). */ +DECL_FINITE_FUNCS (h) + +/* min. */ +DECL_FUNC (h, 01, __FLT16_MIN__) + +/* inf. */ +DECL_FUNC (h, 30, __builtin_inff16 ()) + + +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],-1.0\n" 1 } } */ +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],1.52587890625e-05\n" 1 } } */ +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],3.0517578125e-05\n" 1 } } */ +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],0.00390625\n" 1 } } */ +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],0.0078125\n" 1 } } */ +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],0.0625\n" 1 } } */ +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],0.125\n" 1 } } */ +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],0.25\n" 1 } } */ +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],0.3125\n" 1 } } */ +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],0.375\n" 1 } } */ +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],0.4375\n" 1 } } */ +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],0.5\n" 1 } } */ +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],0.625\n" 1 } } */ +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],0.75\n" 1 } } */ +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],0.875\n" 1 } } */ +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],1.0\n" 1 } } */ +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],1.25\n" 1 } } */ +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],1.5\n" 1 } } */ +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],1.75\n" 1 } } */ +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],2.0\n" 1 } } */ +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],2.5\n" 1 } } */ +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],3.0\n" 1 } } */ +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],4.0\n" 1 } } */ +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],8.0\n" 1 } } */ +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],16.0\n" 1 } } */ +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],128.0\n" 1 } } */ +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],256.0\n" 1 } } */ +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],32768.0\n" 1 } } */ +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],inf\n" 2 } } */ +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],min\n" 1 } } */ +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],nan\n" 1 } } */ + + +/* nan. */ +DECL_FUNC (h, 31, __builtin_nanf16 ("")) + +/* { dg-final { scan-assembler-times "fli\.h\tfa\[0-9\],nan\n" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zfa-fli-7.c b/gcc/testsuite/gcc.target/riscv/zfa-fli-7.c index 912b2bfffff..88189f45dbe 100644 --- a/gcc/testsuite/gcc.target/riscv/zfa-fli-7.c +++ b/gcc/testsuite/gcc.target/riscv/zfa-fli-7.c @@ -25,6 +25,6 @@ DECL_FUNC (h, 2, __builtin_nanf16 ("0")) DECL_FUNC (s, 2, __builtin_nanf ("0")) DECL_FUNC (d, 2, __builtin_nan ("0")) -/* { dg-final { scan-assembler-times "fli\\.h\tfa0,nan\n" 2 } } */ -/* { dg-final { scan-assembler-times "fli\\.s\tfa0,nan\n" 2 } } */ -/* { dg-final { scan-assembler-times "fli\\.d\tfa0,nan\n" 2 } } */ +/* { dg-final { scan-assembler-times "fli\\.h\tfa\[0-9\],nan\n" 2 } } */ +/* { dg-final { scan-assembler-times "fli\\.s\tfa\[0-9\],nan\n" 2 } } */ +/* { dg-final { scan-assembler-times "fli\\.d\tfa\[0-9\],nan\n" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zfa-fli-8.c b/gcc/testsuite/gcc.target/riscv/zfa-fli-8.c index 96a53fd2358..2ef2a1230ef 100644 --- a/gcc/testsuite/gcc.target/riscv/zfa-fli-8.c +++ b/gcc/testsuite/gcc.target/riscv/zfa-fli-8.c @@ -36,4 +36,4 @@ DECL_FUNC (h, 5, -__builtin_nanf16 ("")) DECL_FUNC (s, 5, -__builtin_nanf ("")) DECL_FUNC (d, 5, -__builtin_nan ("")) -/* { dg-final { scan-assembler-not "fli\\.\[hsd]\tfa0,nan\n" } } */ +/* { dg-final { scan-assembler-not "fli\\.\[hsd]\tfa\[0-9\],nan\n" } } */ base-commit: ebffc840f50112196d0d55a384a2c29b08964319 -- 2.17.1