Related Discussion: https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5...@gmail.com/
This patch updates the THEAD instructions to ensure that no insn is left without a type attribute. Tested for regressions using rv32/64 multilib for linux/newlib. gcc/Changelog: * config/riscv/thead.md: Update types Signed-off-by: Edwin Lu <e...@rivosinc.com> --- gcc/config/riscv/thead.md | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md index 29f98dec3a8..6e63cb946e4 100644 --- a/gcc/config/riscv/thead.md +++ b/gcc/config/riscv/thead.md @@ -169,6 +169,7 @@ (define_insn "th_fmv_hw_w_x" "!TARGET_64BIT && TARGET_XTHEADFMV" "fmv.w.x\t%0,%2\n\tth.fmv.hw.x\t%0,%1" [(set_attr "move_type" "move") + (set_attr "type" "fmove") (set_attr "mode" "DF")]) (define_insn "th_fmv_x_w" @@ -178,6 +179,7 @@ (define_insn "th_fmv_x_w" "!TARGET_64BIT && TARGET_XTHEADFMV" "fmv.x.w\t%0,%1" [(set_attr "move_type" "move") + (set_attr "type" "fmove") (set_attr "mode" "DF")]) (define_insn "th_fmv_x_hw" @@ -187,6 +189,7 @@ (define_insn "th_fmv_x_hw" "!TARGET_64BIT && TARGET_XTHEADFMV" "th.fmv.x.hw\t%0,%1" [(set_attr "move_type" "move") + (set_attr "type" "fmove") (set_attr "mode" "DF")]) ;; XTheadMac @@ -322,6 +325,7 @@ (define_insn "*th_mempair_load_<GPR:mode>2" && th_mempair_operands_p (operands, true, <GPR:MODE>mode)" { return th_mempair_output_move (operands, true, <GPR:MODE>mode, UNKNOWN); } [(set_attr "move_type" "load") + (set_attr "type" "load") (set_attr "mode" "<GPR:MODE>")]) ;; MEMPAIR store 64/32 bit @@ -334,6 +338,7 @@ (define_insn "*th_mempair_store_<GPR:mode>2" && th_mempair_operands_p (operands, false, <GPR:MODE>mode)" { return th_mempair_output_move (operands, false, <GPR:MODE>mode, UNKNOWN); } [(set_attr "move_type" "store") + (set_attr "type" "store") (set_attr "mode" "<GPR:MODE>")]) ;; MEMPAIR load DI extended signed SI @@ -346,6 +351,7 @@ (define_insn "*th_mempair_load_extendsidi2" && th_mempair_operands_p (operands, true, SImode)" { return th_mempair_output_move (operands, true, SImode, SIGN_EXTEND); } [(set_attr "move_type" "load") + (set_attr "type" "load") (set_attr "mode" "DI") (set_attr "length" "8")]) @@ -359,6 +365,7 @@ (define_insn "*th_mempair_load_zero_extendsidi2" && th_mempair_operands_p (operands, true, SImode)" { return th_mempair_output_move (operands, true, SImode, ZERO_EXTEND); } [(set_attr "move_type" "load") + (set_attr "type" "load") (set_attr "mode" "DI") (set_attr "length" "8")]) -- 2.34.1