gcc/ChangeLog:
* config/riscv/autovec-opt.md (*cond_<optab><mode><vconvert>):
New combine pattern.
(*cond_<float_cvt><vconvert><mode>): Ditto.
(*cond_<optab><vnconvert><mode>): Ditto.
(*cond_<float_cvt><vnconvert><mode>): Ditto.
(*cond_<optab><mode><vnconvert>): Ditto.
(*cond_<float_cvt><mode><vnconvert>2): Ditto.
* config/riscv/autovec.md (<optab><mode><vconvert>2): Adjust.
(<float_cvt><vconvert><mode>2): Adjust.
(<optab><vnconvert><mode>2): Adjust.
(<float_cvt><vnconvert><mode>2): Adjust.
(<optab><mode><vnconvert>2): Adjust.
(<float_cvt><mode><vnconvert>2): Adjust.
* config/riscv/riscv-v.cc (needs_fp_rounding): Add INT->FP extend.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-1.h: New
test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-2.h: New
test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c:
New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c:
New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c:
New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c:
New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c: New
test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c: New
test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-1.h: New
test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-2.h: New
test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c:
New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c:
New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c:
New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c:
New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c: New
test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c: New
test.
---
gcc/config/riscv/autovec-opt.md | 120 ++++++++++++++++++
gcc/config/riscv/autovec.md | 42 ++++--
gcc/config/riscv/riscv-v.cc | 5 +-
.../autovec/cond/cond_convert_float2int-1.h | 51 ++++++++
.../autovec/cond/cond_convert_float2int-2.h | 50 ++++++++
.../cond/cond_convert_float2int-rv32-1.c | 15 +++
.../cond/cond_convert_float2int-rv32-2.c | 15 +++
.../cond/cond_convert_float2int-rv64-1.c | 15 +++
.../cond/cond_convert_float2int-rv64-2.c | 15 +++
.../cond/cond_convert_float2int_run-1.c | 32 +++++
.../cond/cond_convert_float2int_run-2.c | 31 +++++
.../autovec/cond/cond_convert_int2float-1.h | 45 +++++++
.../autovec/cond/cond_convert_int2float-2.h | 44 +++++++
.../cond/cond_convert_int2float-rv32-1.c | 13 ++
.../cond/cond_convert_int2float-rv32-2.c | 13 ++
.../cond/cond_convert_int2float-rv64-1.c | 13 ++
.../cond/cond_convert_int2float-rv64-2.c | 13 ++
.../cond/cond_convert_int2float_run-1.c | 32 +++++
.../cond/cond_convert_int2float_run-2.c | 31 +++++
19 files changed, 582 insertions(+), 13 deletions(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-1.h
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-2.h
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-1.h
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-2.h
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index ef468bb9df7..1ca5ce97193 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -863,3 +863,123 @@
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
})
+
+;; Combine convert(FP->INT) + vcond_mask
+(define_insn_and_split "*cond_<optab><mode><vconvert>"
+ [(set (match_operand:<VCONVERT> 0 "register_operand")
+ (if_then_else:<VCONVERT>
+ (match_operand:<VM> 1 "register_operand")
+ (any_fix:<VCONVERT>
+ (match_operand:VF 2 "register_operand"))
+ (match_operand:<VCONVERT> 3 "register_operand")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ insn_code icode = code_for_pred (<CODE>, <MODE>mode);
+ rtx ops[] = {operands[0], operands[1], operands[2], operands[3],
+ gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
+ riscv_vector::expand_cond_len_unop (icode, ops);
+ DONE;
+})
+
+;; Combine convert(INT->FP) + vcond_mask
+(define_insn_and_split "*cond_<float_cvt><vconvert><mode>"
+ [(set (match_operand:VF 0 "register_operand")
+ (if_then_else:VF
+ (match_operand:<VM> 1 "register_operand")
+ (any_float:VF
+ (match_operand:<VCONVERT> 2 "register_operand"))
+ (match_operand:VF 3 "register_operand")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ insn_code icode = code_for_pred (<CODE>, <MODE>mode);
+ rtx ops[] = {operands[0], operands[1], operands[2], operands[3],
+ gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
+ riscv_vector::expand_cond_len_unop (icode, ops);
+ DONE;
+})
+
+;; Combine convert(FP->2xINT) + vcond_mask
+(define_insn_and_split "*cond_<optab><vnconvert><mode>"
+ [(set (match_operand:VWCONVERTI 0 "register_operand")
+ (if_then_else:VWCONVERTI
+ (match_operand:<VM> 1 "register_operand")
+ (any_fix:VWCONVERTI
+ (match_operand:<VNCONVERT> 2 "register_operand"))
+ (match_operand:VWCONVERTI 3 "register_operand")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ insn_code icode = code_for_pred_widen (<CODE>, <MODE>mode);
+ rtx ops[] = {operands[0], operands[1], operands[2], operands[3],
+ gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
+ riscv_vector::expand_cond_len_unop (icode, ops);
+ DONE;
+})
+
+;; Combine convert(INT->2xFP) + vcond_mask
+(define_insn_and_split "*cond_<float_cvt><vnconvert><mode>"
+ [(set (match_operand:VF 0 "register_operand")
+ (if_then_else:VF
+ (match_operand:<VM> 1 "register_operand")
+ (any_float:VF
+ (match_operand:<VNCONVERT> 2 "register_operand"))
+ (match_operand:VF 3 "register_operand")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ insn_code icode = code_for_pred_widen (<CODE>, <MODE>mode);
+ rtx ops[] = {operands[0], operands[1], operands[2], operands[3],
+ gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
+ riscv_vector::expand_cond_len_unop (icode, ops);
+ DONE;
+})
+
+;; Combine convert(2xFP->INT) + vcond_mask
+(define_insn_and_split "*cond_<optab><mode><vnconvert>"
+ [(set (match_operand:<VNCONVERT> 0 "register_operand")
+ (if_then_else:<VNCONVERT>
+ (match_operand:<VM> 1 "register_operand")
+ (any_fix:<VNCONVERT>
+ (match_operand:VF 2 "register_operand"))
+ (match_operand:<VNCONVERT> 3 "register_operand")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ insn_code icode = code_for_pred_narrow (<CODE>, <MODE>mode);
+ rtx ops[] = {operands[0], operands[1], operands[2], operands[3],
+ gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
+ riscv_vector::expand_cond_len_unop (icode, ops);
+ DONE;
+})
+
+;; Combine convert(2xINT->FP) + vcond_mask
+(define_insn_and_split "*cond_<float_cvt><mode><vnconvert>2"
+ [(set (match_operand:<VNCONVERT> 0 "register_operand")
+ (if_then_else:<VNCONVERT>
+ (match_operand:<VM> 1 "register_operand")
+ (any_float:<VNCONVERT>
+ (match_operand:VWCONVERTI 2 "register_operand"))
+ (match_operand:<VNCONVERT> 3 "register_operand")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ insn_code icode = code_for_pred_narrow (<CODE>, <MODE>mode);
+ rtx ops[] = {operands[0], operands[1], operands[2], operands[3],
+ gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
+ riscv_vector::expand_cond_len_unop (icode, ops);
+ DONE;
+})
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index a4ac688e373..35e98a6f3f7 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -803,11 +803,14 @@
;; - vfcvt.rtz.x.f.v
;; -------------------------------------------------------------------------
-(define_expand "<optab><mode><vconvert>2"
+(define_insn_and_split "<optab><mode><vconvert>2"
[(set (match_operand:<VCONVERT> 0 "register_operand")
(any_fix:<VCONVERT>
(match_operand:VF 1 "register_operand")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
{
insn_code icode = code_for_pred (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
@@ -822,11 +825,14 @@
;; - vfcvt.f.x.v
;; -------------------------------------------------------------------------
-(define_expand "<float_cvt><vconvert><mode>2"
+(define_insn_and_split "<float_cvt><vconvert><mode>2"
[(set (match_operand:VF 0 "register_operand")
(any_float:VF
(match_operand:<VCONVERT> 1 "register_operand")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
{
insn_code icode = code_for_pred (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP_FRM_DYN,
operands);
@@ -844,11 +850,14 @@
;; - vfwcvt.rtz.xu.f.v
;; - vfwcvt.rtz.x.f.v
;; -------------------------------------------------------------------------
-(define_expand "<optab><vnconvert><mode>2"
+(define_insn_and_split "<optab><vnconvert><mode>2"
[(set (match_operand:VWCONVERTI 0 "register_operand")
(any_fix:VWCONVERTI
(match_operand:<VNCONVERT> 1 "register_operand")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
{
insn_code icode = code_for_pred_widen (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
@@ -862,11 +871,14 @@
;; - vfwcvt.f.xu.v
;; - vfwcvt.f.x.v
;; -------------------------------------------------------------------------
-(define_expand "<float_cvt><vnconvert><mode>2"
+(define_insn_and_split "<float_cvt><vnconvert><mode>2"
[(set (match_operand:VF 0 "register_operand")
(any_float:VF
(match_operand:<VNCONVERT> 1 "register_operand")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
{
insn_code icode = code_for_pred_widen (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
@@ -880,11 +892,14 @@
;; - vfncvt.rtz.xu.f.v
;; - vfncvt.rtz.x.f.v
;; -------------------------------------------------------------------------
-(define_expand "<optab><mode><vnconvert>2"
+(define_insn_and_split "<optab><mode><vnconvert>2"
[(set (match_operand:<VNCONVERT> 0 "register_operand")
(any_fix:<VNCONVERT>
(match_operand:VF 1 "register_operand")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
{
insn_code icode = code_for_pred_narrow (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
@@ -898,11 +913,14 @@
;; - vfncvt.f.xu.w
;; - vfncvt.f.x.w
;; -------------------------------------------------------------------------
-(define_expand "<float_cvt><mode><vnconvert>2"
+(define_insn_and_split "<float_cvt><mode><vnconvert>2"
[(set (match_operand:<VNCONVERT> 0 "register_operand")
(any_float:<VNCONVERT>
(match_operand:VWCONVERTI 1 "register_operand")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
{
insn_code icode = code_for_pred_narrow (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP_FRM_DYN,
operands);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 0f414663620..cdb459f2a47 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2968,7 +2968,10 @@ needs_fp_rounding (unsigned icode, machine_mode mode)
&& icode != maybe_code_for_pred (NEG, mode)
&& icode != maybe_code_for_pred (ABS, mode)
/* narrower-FP -> FP */
- && icode != maybe_code_for_pred_extend (mode);
+ && icode != maybe_code_for_pred_extend (mode)
+ /* narrower-INT -> FP */
+ && icode != maybe_code_for_pred_widen (FLOAT, mode)
+ && icode != maybe_code_for_pred_widen (UNSIGNED_FLOAT, mode);
}
/* Subroutine to expand COND_LEN_* patterns. */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-1.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-1.h
new file mode 100644
index 00000000000..2df68aa2d1e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-1.h
@@ -0,0 +1,51 @@
+#include <stdint.h>
+
+#define DEF_LOOP(OLD_TYPE, NEW_TYPE)
\
+ void __attribute__ ((noipa))
\
+ test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r,
\
+ OLD_TYPE *__restrict a, \
+ NEW_TYPE *__restrict b, \
+ OLD_TYPE *__restrict pred, int n) \
+ {
\
+ for (int i = 0; i < n; ++i)
\
+ {
\
+ r[i] = pred[i] ? (NEW_TYPE) a[i] : b[i]; \
+ }
\
+ }
+
+/* FP -> INT */
+#define TEST_ALL_F2X_SAME(T)
\
+ T (_Float16, uint16_t)
\
+ T (_Float16, int16_t)
\
+ T (float, uint32_t)
\
+ T (float, int32_t)
\
+ T (double, uint64_t)
\
+ T (double, int64_t)
+
+/* FP -> wider-INT */
+#define TEST_ALL_F2X_WIDER(T)
\
+ T (_Float16, uint32_t)
\
+ T (_Float16, int32_t)
\
+ T (_Float16, uint64_t)
\
+ T (_Float16, int64_t)
\
+ T (float, uint64_t)
\
+ T (float, int64_t)
+
+/* FP -> narrower-INT */
+#define TEST_ALL_F2X_NARROWER(T)
\
+ T (_Float16, uint8_t)
\
+ T (_Float16, int8_t)
\
+ T (float, uint8_t)
\
+ T (float, int8_t)
\
+ T (float, uint16_t)
\
+ T (float, int16_t)
\
+ T (double, uint8_t)
\
+ T (double, int8_t)
\
+ T (double, uint16_t)
\
+ T (double, int16_t)
\
+ T (double, uint32_t)
\
+ T (double, int32_t)
+
+TEST_ALL_F2X_SAME (DEF_LOOP)
+TEST_ALL_F2X_WIDER (DEF_LOOP)
+TEST_ALL_F2X_NARROWER (DEF_LOOP)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-2.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-2.h
new file mode 100644
index 00000000000..9735141faa1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-2.h
@@ -0,0 +1,50 @@
+#include <stdint.h>
+
+#define DEF_LOOP(OLD_TYPE, NEW_TYPE)
\
+ void __attribute__ ((noipa))
\
+ test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r,
\
+ OLD_TYPE *__restrict a, NEW_TYPE b, \
+ OLD_TYPE *__restrict pred, int n) \
+ {
\
+ for (int i = 0; i < n; ++i)
\
+ {
\
+ r[i] = pred[i] ? (NEW_TYPE) a[i] : b; \
+ }
\
+ }
+
+/* FP -> INT */
+#define TEST_ALL_F2X_SAME(T)
\
+ T (_Float16, uint16_t)
\
+ T (_Float16, int16_t)
\
+ T (float, uint32_t)
\
+ T (float, int32_t)
\
+ T (double, uint64_t)
\
+ T (double, int64_t)
+
+/* FP -> wider-INT */
+#define TEST_ALL_F2X_WIDER(T)
\
+ T (_Float16, uint32_t)
\
+ T (_Float16, int32_t)
\
+ T (_Float16, uint64_t)
\
+ T (_Float16, int64_t)
\
+ T (float, uint64_t)
\
+ T (float, int64_t)
+
+/* FP -> narrower-INT */
+#define TEST_ALL_F2X_NARROWER(T)
\
+ T (_Float16, uint8_t)
\
+ T (_Float16, int8_t)
\
+ T (float, uint8_t)
\
+ T (float, int8_t)
\
+ T (float, uint16_t)
\
+ T (float, int16_t)
\
+ T (double, uint8_t)
\
+ T (double, int8_t)
\
+ T (double, uint16_t)
\
+ T (double, int16_t)
\
+ T (double, uint32_t)
\
+ T (double, int32_t)
+
+TEST_ALL_F2X_SAME (DEF_LOOP)
+TEST_ALL_F2X_WIDER (DEF_LOOP)
+TEST_ALL_F2X_NARROWER (DEF_LOOP)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c
new file mode 100644
index 00000000000..0702b60c551
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param
riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+
+#include "cond_convert_float2int-1.h"
+
+/* { dg-final { scan-assembler-times
{\tvfcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times
{\tvfcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+
+/* { dg-final { scan-assembler-times
{\tvfwcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times
{\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times
{\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+\n} 2 } } */
+
+/* { dg-final { scan-assembler-times
{\tvfncvt\.rtz\.xu\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times
{\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times
{\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+\n} 6 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c
new file mode 100644
index 00000000000..6eeed28ee6b
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param
riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+
+#include "cond_convert_float2int-2.h"
+
+/* { dg-final { scan-assembler-times
{\tvfcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times
{\tvfcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+
+/* { dg-final { scan-assembler-times
{\tvfwcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times
{\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times
{\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+\n} 2 } } */
+
+/* { dg-final { scan-assembler-times
{\tvfncvt\.rtz\.xu\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times
{\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times
{\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+\n} 6 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c
new file mode 100644
index 00000000000..43f7150fa0b
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param
riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+
+#include "cond_convert_float2int-1.h"
+
+/* { dg-final { scan-assembler-times
{\tvfcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times
{\tvfcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+
+/* { dg-final { scan-assembler-times
{\tvfwcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times
{\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times
{\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+\n} 2 } } */
+
+/* { dg-final { scan-assembler-times
{\tvfncvt\.rtz\.xu\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times
{\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times
{\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+\n} 6 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c
new file mode 100644
index 00000000000..e4a1b175d9f
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param
riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+
+#include "cond_convert_float2int-2.h"
+
+/* { dg-final { scan-assembler-times
{\tvfcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times
{\tvfcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+
+/* { dg-final { scan-assembler-times
{\tvfwcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times
{\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times
{\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+\n} 2 } } */
+
+/* { dg-final { scan-assembler-times
{\tvfncvt\.rtz\.xu\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times
{\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times
{\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+\n} 6 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c
new file mode 100644
index 00000000000..65b54bb3c83
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c
@@ -0,0 +1,32 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable
-fno-vect-cost-model" } */
+
+#include "cond_convert_float2int-1.h"
+
+#define N 99
+
+#define TEST_LOOP(OLD_TYPE, NEW_TYPE)
\
+ {
\
+ NEW_TYPE r[N], b[N];
\
+ OLD_TYPE a[N], pred[N];
\
+ for (int i = 0; i < N; ++i)
\
+ {
\
+ a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \
+ b[i] = (i % 9) * (i % 7 + 1); \
+ pred[i] = (i % 7 < 4); \
+ asm volatile("" ::: "memory"); \
+ }
\
+ test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N);
\
+ for (int i = 0; i < N; ++i)
\
+ if (r[i] != (pred[i] ? (NEW_TYPE) a[i] : b[i]))
\
+ __builtin_abort (); \
+ }
+
+int
+main ()
+{
+ TEST_ALL_F2X_SAME (TEST_LOOP)
+ TEST_ALL_F2X_WIDER (TEST_LOOP)
+ TEST_ALL_F2X_NARROWER (TEST_LOOP)
+ return 0;
+}
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c
new file mode 100644
index 00000000000..030ea2c1964
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c
@@ -0,0 +1,31 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable
-fno-vect-cost-model" } */
+
+#include "cond_convert_float2int-2.h"
+
+#define N 99
+
+#define TEST_LOOP(OLD_TYPE, NEW_TYPE)
\
+ {
\
+ NEW_TYPE r[N], b = 192;
\
+ OLD_TYPE a[N], pred[N];
\
+ for (int i = 0; i < N; ++i)
\
+ {
\
+ a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \
+ pred[i] = (i % 7 < 4); \
+ asm volatile("" ::: "memory"); \
+ }
\
+ test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N);
\
+ for (int i = 0; i < N; ++i)
\
+ if (r[i] != (pred[i] ? (NEW_TYPE) a[i] : b))
\
+ __builtin_abort (); \
+ }
+
+int
+main ()
+{
+ TEST_ALL_F2X_SAME (TEST_LOOP)
+ TEST_ALL_F2X_WIDER (TEST_LOOP)
+ TEST_ALL_F2X_NARROWER (TEST_LOOP)
+ return 0;
+}
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-1.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-1.h
new file mode 100644
index 00000000000..5b0baeece41
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-1.h
@@ -0,0 +1,45 @@
+#include <stdint.h>
+
+#define DEF_LOOP(OLD_TYPE, NEW_TYPE)
\
+ void __attribute__ ((noipa))
\
+ test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r,
\
+ OLD_TYPE *__restrict a, \
+ NEW_TYPE *__restrict b, \
+ OLD_TYPE *__restrict pred, int n) \
+ {
\
+ for (int i = 0; i < n; ++i)
\
+ {
\
+ r[i] = pred[i] ? (NEW_TYPE) a[i] : b[i]; \
+ }
\
+ }
+
+/* INT -> FP */
+#define TEST_ALL_X2F_SAME(T)
\
+ T (uint16_t, _Float16)
\
+ T (int16_t, _Float16)
\
+ T (uint32_t, float)
\
+ T (int32_t, float)
\
+ T (uint64_t, double)
\
+ T (int64_t, double)
+
+/* INT -> wider-FP */
+#define TEST_ALL_X2F_WIDER(T)
\
+ T (uint16_t, float)
\
+ T (int16_t, float)
\
+ T (uint16_t, double)
\
+ T (int16_t, double)
\
+ T (uint32_t, double)
\
+ T (int32_t, double)
+
+/* INT -> narrower-FP */
+#define TEST_ALL_X2F_NARROWER(T)
\
+ T (uint32_t, _Float16)
\
+ T (int32_t, _Float16)
\
+ T (uint64_t, _Float16)
\
+ T (int64_t, _Float16)
\
+ T (uint64_t, float)
\
+ T (int64_t, float)
+
+TEST_ALL_X2F_SAME (DEF_LOOP)
+TEST_ALL_X2F_WIDER (DEF_LOOP)
+TEST_ALL_X2F_NARROWER (DEF_LOOP)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-2.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-2.h
new file mode 100644
index 00000000000..2177c946de8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-2.h
@@ -0,0 +1,44 @@
+#include <stdint.h>
+
+#define DEF_LOOP(OLD_TYPE, NEW_TYPE)
\
+ void __attribute__ ((noipa))
\
+ test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r,
\
+ OLD_TYPE *__restrict a, NEW_TYPE b, \
+ OLD_TYPE *__restrict pred, int n) \
+ {
\
+ for (int i = 0; i < n; ++i)
\
+ {
\
+ r[i] = pred[i] ? (NEW_TYPE) a[i] : b; \
+ }
\
+ }
+
+/* INT -> FP */
+#define TEST_ALL_X2F_SAME(T)
\
+ T (uint16_t, _Float16)
\
+ T (int16_t, _Float16)
\
+ T (uint32_t, float)
\
+ T (int32_t, float)
\
+ T (uint64_t, double)
\
+ T (int64_t, double)
+
+/* INT -> wider-FP */
+#define TEST_ALL_X2F_WIDER(T)
\
+ T (uint16_t, float)
\
+ T (int16_t, float)
\
+ T (uint16_t, double)
\
+ T (int16_t, double)
\
+ T (uint32_t, double)
\
+ T (int32_t, double)
+
+/* INT -> narrower-FP */
+#define TEST_ALL_X2F_NARROWER(T)
\
+ T (uint32_t, _Float16)
\
+ T (int32_t, _Float16)
\
+ T (uint64_t, _Float16)
\
+ T (int64_t, _Float16)
\
+ T (uint64_t, float)
\
+ T (int64_t, float)
+
+TEST_ALL_X2F_SAME (DEF_LOOP)
+TEST_ALL_X2F_WIDER (DEF_LOOP)
+TEST_ALL_X2F_NARROWER (DEF_LOOP)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c
new file mode 100644
index 00000000000..fbb1a28791d
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param
riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+
+#include "cond_convert_int2float-2.h"
+
+/* { dg-final { scan-assembler-times
{\tvfcvt\.f\.xu\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfcvt\.f\.x\.v\tv[0-9]+,v[0-9]+,v0\.t}
3 } } */
+
+/* { dg-final { scan-assembler-times
{\tvfwcvt\.f\.xu\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times
{\tvfwcvt\.f\.x\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
+
+/* { dg-final { scan-assembler-times
{\tvfncvt\.f\.xu\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times
{\tvfncvt\.f\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c
new file mode 100644
index 00000000000..fbb1a28791d
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param
riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+
+#include "cond_convert_int2float-2.h"
+
+/* { dg-final { scan-assembler-times
{\tvfcvt\.f\.xu\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfcvt\.f\.x\.v\tv[0-9]+,v[0-9]+,v0\.t}
3 } } */
+
+/* { dg-final { scan-assembler-times
{\tvfwcvt\.f\.xu\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times
{\tvfwcvt\.f\.x\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
+
+/* { dg-final { scan-assembler-times
{\tvfncvt\.f\.xu\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times
{\tvfncvt\.f\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c
new file mode 100644
index 00000000000..2f85c819709
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param
riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+
+#include "cond_convert_int2float-1.h"
+
+/* { dg-final { scan-assembler-times
{\tvfcvt\.f\.xu\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfcvt\.f\.x\.v\tv[0-9]+,v[0-9]+,v0\.t}
3 } } */
+
+/* { dg-final { scan-assembler-times
{\tvfwcvt\.f\.xu\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times
{\tvfwcvt\.f\.x\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
+
+/* { dg-final { scan-assembler-times
{\tvfncvt\.f\.xu\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times
{\tvfncvt\.f\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c
new file mode 100644
index 00000000000..2f4fdd728bb
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param
riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+
+#include "cond_convert_int2float-2.h"
+
+/* { dg-final { scan-assembler-times
{\tvfcvt\.f\.xu\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfcvt\.f\.x\.v\tv[0-9]+,v[0-9]+,v0\.t}
3 } } */
+
+/* { dg-final { scan-assembler-times
{\tvfwcvt\.f\.xu\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times
{\tvfwcvt\.f\.x\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
+
+/* { dg-final { scan-assembler-times
{\tvfncvt\.f\.xu\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times
{\tvfncvt\.f\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c
new file mode 100644
index 00000000000..10bc06757c1
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c
@@ -0,0 +1,32 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable
-fno-vect-cost-model" } */
+
+#include "cond_convert_int2float-1.h"
+
+#define N 99
+
+#define TEST_LOOP(OLD_TYPE, NEW_TYPE)
\
+ {
\
+ NEW_TYPE r[N], b[N];
\
+ OLD_TYPE a[N], pred[N];
\
+ for (int i = 0; i < N; ++i)
\
+ {
\
+ a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \
+ b[i] = (i % 9) * (i % 7 + 1); \
+ pred[i] = (i % 7 < 4); \
+ asm volatile("" ::: "memory"); \
+ }
\
+ test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N);
\
+ for (int i = 0; i < N; ++i)
\
+ if (r[i] != (pred[i] ? (NEW_TYPE) a[i] : b[i]))
\
+ __builtin_abort (); \
+ }
+
+int
+main ()
+{
+ TEST_ALL_X2F_SAME (TEST_LOOP)
+ TEST_ALL_X2F_WIDER (TEST_LOOP)
+ TEST_ALL_X2F_NARROWER (TEST_LOOP)
+ return 0;
+}
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c
new file mode 100644
index 00000000000..08d27e6dca1
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c
@@ -0,0 +1,31 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable
-fno-vect-cost-model" } */
+
+#include "cond_convert_int2float-2.h"
+
+#define N 99
+
+#define TEST_LOOP(OLD_TYPE, NEW_TYPE)
\
+ {
\
+ NEW_TYPE r[N], b = 192.12;
\
+ OLD_TYPE a[N], pred[N];
\
+ for (int i = 0; i < N; ++i)
\
+ {
\
+ a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \
+ pred[i] = (i % 7 < 4); \
+ asm volatile("" ::: "memory"); \
+ }
\
+ test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N);
\
+ for (int i = 0; i < N; ++i)
\
+ if (r[i] != (pred[i] ? (NEW_TYPE) a[i] : b))
\
+ __builtin_abort (); \
+ }
+
+int
+main ()
+{
+ TEST_ALL_X2F_SAME (TEST_LOOP)
+ TEST_ALL_X2F_WIDER (TEST_LOOP)
+ TEST_ALL_X2F_NARROWER (TEST_LOOP)
+ return 0;
+}
--
2.36.3
