Hi, This patch enables SImode in FP registers on P7. Instruction "fctiw" stores its integer output in an FP register. So SImode in FP register needs be enabled on P7 if we want support "fctiw" on P7.
The test case is in the second patch which implements 32bit inline lrint. Compared to the last version, the main change it to remove disparaging on the alternatives of "fmr". Test shows it doesn't cause regression. https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628435.html Bootstrapped and tested on powerpc64-linux BE and LE with no regressions. ChangeLog rs6000: enable SImode in FP register on P7 gcc/ PR target/88558 * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Enable SImode in FP registers on P7. * config/rs6000/rs6000.md (*movsi_internal1): Add fmr for SImode move between FP registers. Set attribute isa of stfiwx to "*" and attribute of stxsiwx to "p7". patch.diff diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 44b448d2ba6..99085c2cdd7 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -1903,7 +1903,7 @@ rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode) if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD) return 1; - if (TARGET_P8_VECTOR && (mode == SImode)) + if (TARGET_POPCNTD && mode == SImode) return 1; if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode)) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index cdab49fbb91..edf49bd74e3 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -7566,7 +7566,7 @@ (define_split (define_insn "*movsi_internal1" [(set (match_operand:SI 0 "nonimmediate_operand" - "=r, r, + "=r, r, d, r, d, v, m, ?Z, ?Z, r, r, r, r, @@ -7575,7 +7575,7 @@ (define_insn "*movsi_internal1" wa, r, r, *h, *h") (match_operand:SI 1 "input_operand" - "r, U, + "r, U, d, m, ?Z, ?Z, r, d, v, I, L, eI, n, @@ -7588,6 +7588,7 @@ (define_insn "*movsi_internal1" "@ mr %0,%1 la %0,%a1 + fmr %0,%1 lwz%U1%X1 %0,%1 lfiwzx %0,%y1 lxsiwzx %x0,%y1 @@ -7611,7 +7612,7 @@ (define_insn "*movsi_internal1" mt%0 %1 nop" [(set_attr "type" - "*, *, + "*, *, fpsimple, load, fpload, fpload, store, fpstore, fpstore, *, *, *, *, @@ -7620,7 +7621,7 @@ (define_insn "*movsi_internal1" mtvsr, mfvsr, *, *, *") (set_attr "length" - "*, *, + "*, *, *, *, *, *, *, *, *, *, *, *, 8, @@ -7629,9 +7630,9 @@ (define_insn "*movsi_internal1" *, *, *, *, *") (set_attr "isa" - "*, *, - *, p8v, p8v, - *, p8v, p8v, + "*, *, *, + *, p7, p8v, + *, *, p8v, *, *, p10, *, p8v, p9v, p9v, p8v, p9v, p8v, p9v,
