LGTM
Christoph Muellner <christoph.muell...@vrull.eu>於 2023年9月8日 週五，14:00寫道：
> From: Christoph Müllner <christoph.muell...@vrull.eu>
>
> Recently three SPEC CPU 2017 benchmarks broke when using xtheadbb:
> * 500.perlbench_r
> * 525.x264_r
> * 557.xz_r
>
> Tracing the issue down revealed, that we emit a 'th.ext xN,xN,15,0'
> for a extendqi<SUPERQI> insn, which is obviously wrong.
> This patch splits the common 'extend<SHORT:mode><SUPERQI:mode>2_th_ext'
> insn into two 'extendqi<SUPERQI>' and 'extendhi<SUPERQI>' insns,
> which emit the right extension instruction.
> Additionally, this patch adds test cases for these insns.
>
> Signed-off-by: Christoph Müllner <christoph.muell...@vrull.eu>
>
> gcc/ChangeLog:
>
> * config/riscv/thead.md
> (*extend<SHORT:mode><SUPERQI:mode>2_th_ext):
> Remove broken INSN.
> (*extendhi<SUPERQI:mode>2_th_ext): New INSN.
> (*extendqi<SUPERQI:mode>2_th_ext): New INSN.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/xtheadbb-ext-2.c: New test.
> * gcc.target/riscv/xtheadbb-ext-3.c: New test.
> ---
> gcc/config/riscv/thead.md | 17 ++++++++++++++---
> gcc/testsuite/gcc.target/riscv/xtheadbb-ext-2.c | 12 ++++++++++++
> gcc/testsuite/gcc.target/riscv/xtheadbb-ext-3.c | 12 ++++++++++++
> 3 files changed, 38 insertions(+), 3 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ext-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ext-3.c
>
> diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
> index 29f98dec3a8..05d1b32bd94 100644
> --- a/gcc/config/riscv/thead.md
> +++ b/gcc/config/riscv/thead.md
> @@ -58,14 +58,25 @@ (define_insn "*th_ext<mode>4"
> [(set_attr "type" "bitmanip")
> (set_attr "mode" "<GPR:MODE>")])
>
> -(define_insn "*extend<SHORT:mode><SUPERQI:mode>2_th_ext"
> +(define_insn "*extendhi<SUPERQI:mode>2_th_ext"
> [(set (match_operand:SUPERQI 0 "register_operand" "=r,r")
> (sign_extend:SUPERQI
> - (match_operand:SHORT 1 "nonimmediate_operand" "r,m")))]
> + (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
> "TARGET_XTHEADBB"
> "@
> th.ext\t%0,%1,15,0
> - l<SHORT:size>\t%0,%1"
> + lh\t%0,%1"
> + [(set_attr "type" "bitmanip,load")
> + (set_attr "mode" "<SUPERQI:MODE>")])
> +
> +(define_insn "*extendqi<SUPERQI:mode>2_th_ext"
> + [(set (match_operand:SUPERQI 0 "register_operand" "=r,r")
> + (sign_extend:SUPERQI
> + (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
> + "TARGET_XTHEADBB"
> + "@
> + th.ext\t%0,%1,7,0
> + lb\t%0,%1"
> [(set_attr "type" "bitmanip,load")
> (set_attr "mode" "<SUPERQI:MODE>")])
>
> diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-2.c
> b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-2.c
> new file mode 100644
> index 00000000000..4645b9c56df
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-2.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc_xtheadbb" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_xtheadbb" { target { rv32 } } } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" "-Oz" } } */
> +
> +signed long extqi(signed char i)
> +{
> + return --i;
> +}
> +
> +/* { dg-final { scan-assembler "th.ext\ta\[0-9\]+,a\[0-9\]+,7,0" } } */
> +/* { dg-final { scan-assembler-not "th.ext\ta\[0-9\]+,a\[0-9\]+,15,0" } }
> */
> diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-3.c
> b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-3.c
> new file mode 100644
> index 00000000000..2c9ebbc563a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-3.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc_xtheadbb" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_xtheadbb" { target { rv32 } } } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" "-Oz" } } */
> +
> +signed long exthi(signed short i)
> +{
> + return --i;
> +}
> +
> +/* { dg-final { scan-assembler "th.ext\ta\[0-9\]+,a\[0-9\]+,15,0" } } */
> +/* { dg-final { scan-assembler-not "th.ext\ta\[0-9\]+,a\[0-9\]+,7,0" } }
> */
> --
> 2.41.0
>
>
