Hi Ajit,
on 2023/8/31 18:44, Ajit Agarwal via Gcc-patches wrote:
>
> This patch removes zero extension from vctzlsbb as it already zero extends.
> Bootstrapped and regtested on powerpc64-linux-gnu.
>
> Thanks & Regards
> Ajit
>
> rs6000: unnecessary clear after vctzlsbb in vec_first_match_or_eos_index
>
> For rs6000 target we dont need zero_extend after vctzlsbb as vctzlsbb
> already zero extend.
>
> 2023-08-31 Ajit Kumar Agarwal <aagar...@linux.ibm.com>
>
> gcc/ChangeLog:
>
> * config/rs6000/vsx.md: Add new pattern.
Nit: we can offer the pattern name, such as:
* config/rs6000/vsx.md (vctzlsbb_zext_<mode>): New define_insn.
>
> gcc/testsuite/ChangeLog:
>
> * g++.target/powerpc/altivec-19.C: New testcase.
> ---
> gcc/config/rs6000/vsx.md | 17 ++++++++++++++---
> gcc/testsuite/g++.target/powerpc/altivec-19.C | 11 +++++++++++
> 2 files changed, 25 insertions(+), 3 deletions(-)
> create mode 100644 gcc/testsuite/g++.target/powerpc/altivec-19.C
>
> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
> index 19abfeb565a..09d21a6d00a 100644
> --- a/gcc/config/rs6000/vsx.md
> +++ b/gcc/config/rs6000/vsx.md
> @@ -5846,11 +5846,22 @@
> [(set_attr "type" "vecsimple")])
>
> ;; Vector Count Trailing Zero Least-Significant Bits Byte
> -(define_insn "vctzlsbb_<mode>"
> - [(set (match_operand:SI 0 "register_operand" "=r")
> +(define_insn "vctzlsbbzext_<mode>"
Nit: s/vctzlsbbzext_/vctzlsbb_zext_/, it's read better to separate
the mnemonic (vctzlsbb).
> + [(set (match_operand:DI 0 "register_operand" "=r")
> + (zero_extend:DI
> (unspec:SI
> [(match_operand:VSX_EXTRACT_I 1 "altivec_register_operand" "v")]
> - UNSPEC_VCTZLSBB))]
> + UNSPEC_VCTZLSBB)))]
> + "TARGET_P9_VECTOR"
> + "vctzlsbb %0,%1"
> + [(set_attr "type" "vecsimple")])
> +
> +;; Vector Count Trailing Zero Least-Significant Bits Byte
> +(define_insn "vctzlsbb_<mode>"
> + [(set (match_operand:SI 0 "register_operand" "=r")
> + (unspec:SI
> + [(match_operand:VSX_EXTRACT_I 1 "altivec_register_operand" "v")]
> + UNSPEC_VCTZLSBB))]
> "TARGET_P9_VECTOR"
> "vctzlsbb %0,%1"
> [(set_attr "type" "vecsimple")])
> diff --git a/gcc/testsuite/g++.target/powerpc/altivec-19.C
> b/gcc/testsuite/g++.target/powerpc/altivec-19.C
> new file mode 100644
> index 00000000000..2d630b2fc1f
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/powerpc/altivec-19.C
> @@ -0,0 +1,11 @@
> +/* { dg-do compile { target { powerpc*-*-* } } } */
Nit: Can be simpler with /* { dg-do compile } */
as the target requirement is always satisfied in powerpc
test suite.
> +/* { dg-require-effective-target lp64 } */
This line can be removed as this case and its checking doesn't
require 64 bit env.
> +/* { dg-require-effective-target powerpc_p9vector_ok } */
> +/* { dg-options "-mcpu=power9 -O2 " } */
Use -mdejagnu-cpu=power9 instead of -mcpu=power9, it can always
take effect when mixing some other -mcpu=* from the RUN FLAGS.
> +
> +#include <altivec.h>
> +
> +unsigned int foo (vector unsigned char a, vector unsigned char b) {
> + return vec_first_match_or_eos_index (a, b);
> +}
> +/* { dg-final { scan-assembler-not "rldicl" } } */
Nit: Maybe with \m and \M like:
/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
BR,
Kewen
