Since RISC-V use vsseg5 which is the vect_store_lanes with stride 5 if failed on RISC-V.
gcc/testsuite/ChangeLog: * gcc.dg/vect/slp-34.c: Block check for vect_strided5. --- gcc/testsuite/gcc.dg/vect/slp-34.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.dg/vect/slp-34.c b/gcc/testsuite/gcc.dg/vect/slp-34.c index 41832d7f519..53b8284d084 100644 --- a/gcc/testsuite/gcc.dg/vect/slp-34.c +++ b/gcc/testsuite/gcc.dg/vect/slp-34.c @@ -57,5 +57,5 @@ int main (void) } /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ -/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target {! vect_strided5 } } } } */ -- 2.36.3