From: Haochen Jiang <haochen.ji...@intel.com> gcc/ChangeLog:
* config/i386/i386.opt: Allow -mno-evex512. gcc/testsuite/ChangeLog: * gcc.target/i386/noevex512-1.c: New test. * gcc.target/i386/noevex512-2.c: Ditto. * gcc.target/i386/noevex512-3.c: Ditto. --- gcc/config/i386/i386.opt | 2 +- gcc/testsuite/gcc.target/i386/noevex512-1.c | 13 +++++++++++++ gcc/testsuite/gcc.target/i386/noevex512-2.c | 13 +++++++++++++ gcc/testsuite/gcc.target/i386/noevex512-3.c | 13 +++++++++++++ 4 files changed, 40 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/i386/noevex512-1.c create mode 100644 gcc/testsuite/gcc.target/i386/noevex512-2.c create mode 100644 gcc/testsuite/gcc.target/i386/noevex512-3.c diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 6d8601b1f75..34fc167af82 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -1312,5 +1312,5 @@ Target Alias(mtune-ctrl=, use_scatter, ^use_scatter) Enable vectorization for scatter instruction. mevex512 -Target RejectNegative Mask(ISA2_EVEX512) Var(ix86_isa_flags2) Save +Target Mask(ISA2_EVEX512) Var(ix86_isa_flags2) Save Support 512 bit vector built-in functions and code generation. diff --git a/gcc/testsuite/gcc.target/i386/noevex512-1.c b/gcc/testsuite/gcc.target/i386/noevex512-1.c new file mode 100644 index 00000000000..7fd45f15be6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/noevex512-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -march=x86-64 -mavx512f -mno-evex512 -Wno-psabi" } */ +/* { dg-final { scan-assembler-not ".%zmm" } } */ + +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); + +__m512d +foo () +{ + __m512d a, b; + a = a + b; + return a; +} diff --git a/gcc/testsuite/gcc.target/i386/noevex512-2.c b/gcc/testsuite/gcc.target/i386/noevex512-2.c new file mode 100644 index 00000000000..1c206e385d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/noevex512-2.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64 -mavx512bw -mno-evex512" } */ + +#include <immintrin.h> + +long long +foo (long long c) +{ + register long long a __asm ("k7") = c; + long long b = foo (a); + asm volatile ("" : "+k" (b)); /* { dg-error "inconsistent operand constraints in an 'asm'" } */ + return b; +} diff --git a/gcc/testsuite/gcc.target/i386/noevex512-3.c b/gcc/testsuite/gcc.target/i386/noevex512-3.c new file mode 100644 index 00000000000..10e00c2d61c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/noevex512-3.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64 -Wno-psabi -mavx512f" } */ +/* { dg-final { scan-assembler-not ".%zmm" } } */ + +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); + +__attribute__ ((target ("no-evex512"))) __m512d +foo () +{ + __m512d a, b; + a = a + b; + return a; +} -- 2.31.1