From: Kong Lingling <lingling.k...@intel.com>
For APX, as we extended the GENERAL_REG_CLASS, new constraints are
needed to restrict insns that cannot adopt EGPR either in its reg or
memory operands. We added a series of constraints for general/backend
ones that related to GPR usage. All of them are prefixed with "j" to
indicate the constraints does not allow EGPR.
gcc/ChangeLog:
* config/i386/constraints.md (jr): New register constraint
that prohibits EGPR.
(jR): Constraint that force usage of EGPR.
(jm): New memory constraint that prohibits EGPR.
(ja): Likewise for Bm constraint.
(jb): Likewise for Tv constraint.
(j<): New auto-dec memory constraint that prohibits EGPR.
(j>): Likewise for ">" constraint.
(jo): Likewise for "o" constraint.
(jv): Likewise for "V" constraint.
(jp): Likewise for "p" constraint.
* config/i386/i386.h (enum reg_class): Add new reg class
GENERAL_GPR16.
Co-authored-by: Hongyu Wang <hongyu.w...@intel.com>
Co-authored-by: Hongtao Liu <hongtao....@intel.com>
---
gcc/config/i386/constraints.md | 59 +++++++++++++++++++++++++++++++++-
gcc/config/i386/i386.h | 4 +++
2 files changed, 62 insertions(+), 1 deletion(-)
diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md
index fd490f39110..36c268d7f9b 100644
--- a/gcc/config/i386/constraints.md
+++ b/gcc/config/i386/constraints.md
@@ -19,7 +19,7 @@
;;; Unused letters:
;;; H
-;;; h j z
+;;; j z
;; Integer register constraints.
;; It is not necessary to define 'r' here.
@@ -371,3 +371,60 @@ (define_address_constraint "Tv"
(define_address_constraint "Ts"
"Address operand without segment register"
(match_operand 0 "address_no_seg_operand"))
+
+;; Constraint that force to use EGPR, can only adopt to register class.
+(define_register_constraint "jR" "GENERAL_REGS")
+
+(define_register_constraint "jr"
+ "TARGET_APX_EGPR ? GENERAL_GPR16 : GENERAL_REGS")
+
+(define_memory_constraint "jm"
+ "@internal memory operand without GPR32."
+ (and (match_operand 0 "memory_operand")
+ (not (and (match_test "TARGET_APX_EGPR")
+ (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
+
+(define_constraint "j<"
+ "@internal auto-dec memory operand without GPR32."
+ (and (and (match_code "mem")
+ (ior (match_test "GET_CODE (XEXP (op, 0)) == PRE_DEC")
+ (match_test "GET_CODE (XEXP (op, 0)) == POST_DEC")))
+ (not (and (match_test "TARGET_APX_EGPR")
+ (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
+
+(define_constraint "j>"
+ "@internal auto-dec memory operand without GPR32."
+ (and (and (match_code "mem")
+ (ior (match_test "GET_CODE (XEXP (op, 0)) == PRE_INC")
+ (match_test "GET_CODE (XEXP (op, 0)) == POST_INC")))
+ (not (and (match_test "TARGET_APX_EGPR")
+ (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
+
+(define_memory_constraint "jo"
+ "@internal offsetable memory operand without GPR32."
+ (and (and (match_code "mem")
+ (match_test "offsettable_nonstrict_memref_p (op)"))
+ (not (and (match_test "TARGET_APX_EGPR")
+ (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
+
+(define_constraint "jV"
+ "@internal non-offsetable memory operand without GPR32."
+ (and (and (match_code "mem")
+ (match_test "memory_address_addr_space_p (GET_MODE (op),
+ XEXP (op, 0),
+ MEM_ADDR_SPACE (op))")
+ (not (match_test "offsettable_nonstrict_memref_p (op)")))
+ (not (and (match_test "TARGET_APX_EGPR")
+ (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
+
+(define_address_constraint "jp"
+ "@internal general address operand without GPR32"
+ (and (match_test "address_operand (op, VOIDmode)")
+ (not (and (match_test "TARGET_APX_EGPR")
+ (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
+
+(define_special_memory_constraint "ja"
+ "@internal vector memory operand without GPR32."
+ (and (match_operand 0 "vector_memory_operand")
+ (not (and (match_test "TARGET_APX_EGPR")
+ (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 215f6b8db55..66b8764e82b 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -1295,6 +1295,8 @@ enum reg_class
%r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15
%r16 %r17 %r18 %r19 %r20 %r21 %r22 %r23
%r24 %r25 %r26 %r27 %r28 %r29 %r30 %r31 */
+ GENERAL_GPR16, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp
+ %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */
FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
FLOAT_REGS,
SSE_FIRST_REG,
@@ -1357,6 +1359,7 @@ enum reg_class
"INDEX_REGS", \
"LEGACY_REGS", \
"GENERAL_REGS", \
+ "GENERAL_GPR16", \
"FP_TOP_REG", "FP_SECOND_REG", \
"FLOAT_REGS", \
"SSE_FIRST_REG", \
@@ -1395,6 +1398,7 @@ enum reg_class
{ 0x7f, 0xff0, 0x0 }, /* INDEX_REGS */ \
{ 0x900ff, 0x0, 0x0 }, /* LEGACY_REGS */ \
{ 0x900ff, 0xff0, 0xffff000 }, /* GENERAL_REGS */
\
+ { 0x900ff, 0xff0, 0x0 }, /* GENERAL_GPR16 */ \
{ 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \
{ 0x200, 0x0, 0x0 }, /* FP_SECOND_REG */ \
{ 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \
--
2.31.1
