Confirm it is a latent bug already existed long time ago but we were lucky that we didn't trigger this issue before.
This patch didn't involve a new bug. Li pan from intel will send a patch fix it soon. Thanks for report. juzhe.zh...@rivai.ai From: Edwin Lu Date: 2023-09-23 06:38 To: Juzhe-Zhong; gcc-patches CC: patrick; gnu-toolchain Subject: Re: [Committed] RISC-V: Support VLS INT <-> FP conversions Hi Juzhe, I was testing this patch and found it introduced a gfortran regression in gfortran.dg/host_assoc_function_7.f90. More info here: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111545 Edwin On 9/20/2023 7:17 PM, Juzhe-Zhong wrote: > Support INT <-> FP VLS auto-vectorization patterns. > > Regression passed. > Committed. > > gcc/ChangeLog: > > * config/riscv/autovec.md: Extend VLS modes. > * config/riscv/vector-iterators.md: Ditto. > * config/riscv/vector.md: Ditto. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/autovec/vls/convert-1.c: New test. > * gcc.target/riscv/rvv/autovec/vls/convert-10.c: New test. > * gcc.target/riscv/rvv/autovec/vls/convert-11.c: New test. > * gcc.target/riscv/rvv/autovec/vls/convert-12.c: New test. > * gcc.target/riscv/rvv/autovec/vls/convert-2.c: New test. > * gcc.target/riscv/rvv/autovec/vls/convert-3.c: New test. > * gcc.target/riscv/rvv/autovec/vls/convert-4.c: New test. > * gcc.target/riscv/rvv/autovec/vls/convert-5.c: New test. > * gcc.target/riscv/rvv/autovec/vls/convert-6.c: New test. > * gcc.target/riscv/rvv/autovec/vls/convert-7.c: New test. > * gcc.target/riscv/rvv/autovec/vls/convert-8.c: New test. > * gcc.target/riscv/rvv/autovec/vls/convert-9.c: New test. > > --- > gcc/config/riscv/autovec.md | 12 +- > gcc/config/riscv/vector-iterators.md | 202 ++++++++++++++++++ > gcc/config/riscv/vector.md | 20 +- > .../riscv/rvv/autovec/vls/convert-1.c | 74 +++++++ > .../riscv/rvv/autovec/vls/convert-10.c | 80 +++++++ > .../riscv/rvv/autovec/vls/convert-11.c | 54 +++++ > .../riscv/rvv/autovec/vls/convert-12.c | 36 ++++ > .../riscv/rvv/autovec/vls/convert-2.c | 74 +++++++ > .../riscv/rvv/autovec/vls/convert-3.c | 58 +++++ > .../riscv/rvv/autovec/vls/convert-4.c | 36 ++++ > .../riscv/rvv/autovec/vls/convert-5.c | 80 +++++++ > .../riscv/rvv/autovec/vls/convert-6.c | 55 +++++ > .../riscv/rvv/autovec/vls/convert-7.c | 37 ++++ > .../riscv/rvv/autovec/vls/convert-8.c | 58 +++++ > .../riscv/rvv/autovec/vls/convert-9.c | 22 ++ > 15 files changed, 882 insertions(+), 16 deletions(-) > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-1.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-10.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-11.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-12.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-2.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-3.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-4.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-5.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-6.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-7.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-8.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-9.c > > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md > index 75ed7ae4f2e..55c0a04df3b 100644 > --- a/gcc/config/riscv/autovec.md > +++ b/gcc/config/riscv/autovec.md > @@ -847,7 +847,7 @@ > (define_insn_and_split "<optab><mode><vconvert>2" > [(set (match_operand:<VCONVERT> 0 "register_operand") > (any_fix:<VCONVERT> > - (match_operand:VF 1 "register_operand")))] > + (match_operand:V_VLSF 1 "register_operand")))] > "TARGET_VECTOR && can_create_pseudo_p ()" > "#" > "&& 1" > @@ -868,8 +868,8 @@ > ;; ------------------------------------------------------------------------- > > (define_insn_and_split "<float_cvt><vconvert><mode>2" > - [(set (match_operand:VF 0 "register_operand") > - (any_float:VF > + [(set (match_operand:V_VLSF 0 "register_operand") > + (any_float:V_VLSF > (match_operand:<VCONVERT> 1 "register_operand")))] > "TARGET_VECTOR && can_create_pseudo_p ()" > "#" > @@ -916,8 +916,8 @@ > ;; - vfwcvt.f.x.v > ;; ------------------------------------------------------------------------- > (define_insn_and_split "<float_cvt><vnconvert><mode>2" > - [(set (match_operand:VF 0 "register_operand") > - (any_float:VF > + [(set (match_operand:V_VLSF 0 "register_operand") > + (any_float:V_VLSF > (match_operand:<VNCONVERT> 1 "register_operand")))] > "TARGET_VECTOR && can_create_pseudo_p ()" > "#" > @@ -940,7 +940,7 @@ > (define_insn_and_split "<optab><mode><vnconvert>2" > [(set (match_operand:<VNCONVERT> 0 "register_operand") > (any_fix:<VNCONVERT> > - (match_operand:VF 1 "register_operand")))] > + (match_operand:V_VLSF 1 "register_operand")))] > "TARGET_VECTOR && can_create_pseudo_p ()" > "#" > "&& 1" > diff --git a/gcc/config/riscv/vector-iterators.md > b/gcc/config/riscv/vector-iterators.md > index 053d84c0c7d..19f3ec3ef74 100644 > --- a/gcc/config/riscv/vector-iterators.md > +++ b/gcc/config/riscv/vector-iterators.md > @@ -1037,6 +1037,28 @@ > (RVVM4DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32") > (RVVM2DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32") > (RVVM1DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32") > + > + (V1SI "TARGET_VECTOR_VLS && TARGET_ZVFH") > + (V2SI "TARGET_VECTOR_VLS && TARGET_ZVFH") > + (V4SI "TARGET_VECTOR_VLS && TARGET_ZVFH") > + (V8SI "TARGET_VECTOR_VLS && TARGET_ZVFH") > + (V16SI "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 64") > + (V32SI "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 128") > + (V64SI "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 256") > + (V128SI "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 512") > + (V256SI "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 1024") > + (V512SI "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 2048") > + (V1024SI "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 4096") > + (V1DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && > TARGET_VECTOR_ELEN_FP_32") > + (V2DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && > TARGET_VECTOR_ELEN_FP_32") > + (V4DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && > TARGET_VECTOR_ELEN_FP_32") > + (V8DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64") > + (V16DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") > + (V32DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256") > + (V64DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512") > + (V128DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024") > + (V256DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048") > + (V512DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && > TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096") > ]) > > (define_mode_iterator VQEXTI [ > @@ -2635,12 +2657,80 @@ > (RVVM8HF "RVVM8HI") (RVVM4HF "RVVM4HI") (RVVM2HF "RVVM2HI") (RVVM1HF > "RVVM1HI") (RVVMF2HF "RVVMF2HI") (RVVMF4HF "RVVMF4HI") > (RVVM8SF "RVVM8SI") (RVVM4SF "RVVM4SI") (RVVM2SF "RVVM2SI") (RVVM1SF > "RVVM1SI") (RVVMF2SF "RVVMF2SI") > (RVVM8DF "RVVM8DI") (RVVM4DF "RVVM4DI") (RVVM2DF "RVVM2DI") (RVVM1DF > "RVVM1DI") > + > + (V1HF "V1HI") > + (V2HF "V2HI") > + (V4HF "V4HI") > + (V8HF "V8HI") > + (V16HF "V16HI") > + (V32HF "V32HI") > + (V64HF "V64HI") > + (V128HF "V128HI") > + (V256HF "V256HI") > + (V512HF "V512HI") > + (V1024HF "V1024HI") > + (V2048HF "V2048HI") > + (V1SF "V1SI") > + (V2SF "V2SI") > + (V4SF "V4SI") > + (V8SF "V8SI") > + (V16SF "V16SI") > + (V32SF "V32SI") > + (V64SF "V64SI") > + (V128SF "V128SI") > + (V256SF "V256SI") > + (V512SF "V512SI") > + (V1024SF "V1024SI") > + (V1DF "V1DI") > + (V2DF "V2DI") > + (V4DF "V4DI") > + (V8DF "V8DI") > + (V16DF "V16DI") > + (V32DF "V32DI") > + (V64DF "V64DI") > + (V128DF "V128DI") > + (V256DF "V256DI") > + (V512DF "V512DI") > ]) > > (define_mode_attr vconvert [ > (RVVM8HF "rvvm8hi") (RVVM4HF "rvvm4hi") (RVVM2HF "rvvm2hi") (RVVM1HF > "rvvm1hi") (RVVMF2HF "rvvmf2hi") (RVVMF4HF "rvvmf4hi") > (RVVM8SF "rvvm8si") (RVVM4SF "rvvm4si") (RVVM2SF "rvvm2si") (RVVM1SF > "rvvm1si") (RVVMF2SF "rvvmf2si") > (RVVM8DF "rvvm8di") (RVVM4DF "rvvm4di") (RVVM2DF "rvvm2di") (RVVM1DF > "rvvm1di") > + > + (V1HF "v1hi") > + (V2HF "v2hi") > + (V4HF "v4hi") > + (V8HF "v8hi") > + (V16HF "v16hi") > + (V32HF "v32hi") > + (V64HF "v64hi") > + (V128HF "v128hi") > + (V256HF "v256hi") > + (V512HF "v512hi") > + (V1024HF "v1024hi") > + (V2048HF "v2048hi") > + (V1SF "v1si") > + (V2SF "v2si") > + (V4SF "v4si") > + (V8SF "v8si") > + (V16SF "v16si") > + (V32SF "v32si") > + (V64SF "v64si") > + (V128SF "v128si") > + (V256SF "v256si") > + (V512SF "v512si") > + (V1024SF "v1024si") > + (V1DF "v1di") > + (V2DF "v2di") > + (V4DF "v4di") > + (V8DF "v8di") > + (V16DF "v16di") > + (V32DF "v32di") > + (V64DF "v64di") > + (V128DF "v128di") > + (V256DF "v256di") > + (V512DF "v512di") > ]) > > (define_mode_attr VNCONVERT [ > @@ -2651,6 +2741,62 @@ > > (RVVM8DI "RVVM4SF") (RVVM4DI "RVVM2SF") (RVVM2DI "RVVM1SF") (RVVM1DI > "RVVMF2SF") > (RVVM8DF "RVVM4SI") (RVVM4DF "RVVM2SI") (RVVM2DF "RVVM1SI") (RVVM1DF > "RVVMF2SI") > + > + (V1SI "V1HF") > + (V2SI "V2HF") > + (V4SI "V4HF") > + (V8SI "V8HF") > + (V16SI "V16HF") > + (V32SI "V32HF") > + (V64SI "V64HF") > + (V128SI "V128HF") > + (V256SI "V256HF") > + (V512SI "V512HF") > + (V1024SI "V1024HF") > + (V1DI "V1SF") > + (V2DI "V2SF") > + (V4DI "V4SF") > + (V8DI "V8SF") > + (V16DI "V16SF") > + (V32DI "V32SF") > + (V64DI "V64SF") > + (V128DI "V128SF") > + (V256DI "V256SF") > + (V512DI "V512SF") > + > + (V1HF "V1QI") > + (V2HF "V2QI") > + (V4HF "V4QI") > + (V8HF "V8QI") > + (V16HF "V16QI") > + (V32HF "V32QI") > + (V64HF "V64QI") > + (V128HF "V128QI") > + (V256HF "V256QI") > + (V512HF "V512QI") > + (V1024HF "V1024QI") > + (V2048HF "V2048QI") > + (V1SF "V1HI") > + (V2SF "V2HI") > + (V4SF "V4HI") > + (V8SF "V8HI") > + (V16SF "V16HI") > + (V32SF "V32HI") > + (V64SF "V64HI") > + (V128SF "V128HI") > + (V256SF "V256HI") > + (V512SF "V512HI") > + (V1024SF "V1024HI") > + (V1DF "V1SI") > + (V2DF "V2SI") > + (V4DF "V4SI") > + (V8DF "V8SI") > + (V16DF "V16SI") > + (V32DF "V32SI") > + (V64DF "V64SI") > + (V128DF "V128SI") > + (V256DF "V256SI") > + (V512DF "V512SI") > ]) > > (define_mode_attr vnconvert [ > @@ -2661,6 +2807,62 @@ > > (RVVM8DI "rvvm4sf") (RVVM4DI "rvvm2sf") (RVVM2DI "rvvm1sf") (RVVM1DI > "rvvmf2sf") > (RVVM8DF "rvvm4si") (RVVM4DF "rvvm2si") (RVVM2DF "rvvm1si") (RVVM1DF > "rvvmf2si") > + > + (V1SI "v1hf") > + (V2SI "v2hf") > + (V4SI "v4hf") > + (V8SI "v8hf") > + (V16SI "v16hf") > + (V32SI "v32hf") > + (V64SI "v64hf") > + (V128SI "v128hf") > + (V256SI "v256hf") > + (V512SI "v512hf") > + (V1024SI "v1024hf") > + (V1DI "v1sf") > + (V2DI "v2sf") > + (V4DI "v4sf") > + (V8DI "v8sf") > + (V16DI "v16sf") > + (V32DI "v32sf") > + (V64DI "v64sf") > + (V128DI "v128sf") > + (V256DI "v256sf") > + (V512DI "v512sf") > + > + (V1HF "v1qi") > + (V2HF "v2qi") > + (V4HF "v4qi") > + (V8HF "v8qi") > + (V16HF "v16qi") > + (V32HF "v32qi") > + (V64HF "v64qi") > + (V128HF "v128qi") > + (V256HF "v256qi") > + (V512HF "v512qi") > + (V1024HF "v1024qi") > + (V2048HF "v2048qi") > + (V1SF "v1hi") > + (V2SF "v2hi") > + (V4SF "v4hi") > + (V8SF "v8hi") > + (V16SF "v16hi") > + (V32SF "v32hi") > + (V64SF "v64hi") > + (V128SF "v128hi") > + (V256SF "v256hi") > + (V512SF "v512hi") > + (V1024SF "v1024hi") > + (V1DF "v1si") > + (V2DF "v2si") > + (V4DF "v4si") > + (V8DF "v8si") > + (V16DF "v16si") > + (V32DF "v32si") > + (V64DF "v64si") > + (V128DF "v128si") > + (V256DF "v256si") > + (V512DF "v512si") > ]) > > (define_mode_attr VDEMOTE [ > diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md > index f66ffebba24..79c4a4bda53 100644 > --- a/gcc/config/riscv/vector.md > +++ b/gcc/config/riscv/vector.md > @@ -7451,7 +7451,7 @@ > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (any_fix:<VCONVERT> > - (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) > + (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")) > (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))] > "TARGET_VECTOR" > "vfcvt.rtz.x<u>.f.v\t%0,%3%p1" > @@ -7459,8 +7459,8 @@ > (set_attr "mode" "<MODE>")]) > > (define_insn "@pred_<float_cvt><mode>" > - [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, > vr") > - (if_then_else:VF > + [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, > vr, vr") > + (if_then_else:V_VLSF > (unspec:<VM> > [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") > (match_operand 4 "vector_length_operand" " rK, rK, rK, rK") > @@ -7471,9 +7471,9 @@ > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM) > (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > - (any_float:VF > + (any_float:V_VLSF > (match_operand:<VCONVERT> 3 "register_operand" " vr, vr, vr, vr")) > - (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] > + (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, > 0")))] > "TARGET_VECTOR" > "vfcvt.f.x<u>.v\t%0,%3%p1" > [(set_attr "type" "vfcvtitof") > @@ -7531,8 +7531,8 @@ > (set_attr "mode" "<VNCONVERT>")]) > > (define_insn "@pred_widen_<float_cvt><mode>" > - [(set (match_operand:VF 0 "register_operand" "=&vr, &vr") > - (if_then_else:VF > + [(set (match_operand:V_VLSF 0 "register_operand" "=&vr, > &vr") > + (if_then_else:V_VLSF > (unspec:<VM> > [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1") > (match_operand 4 "vector_length_operand" " rK, rK") > @@ -7541,9 +7541,9 @@ > (match_operand 7 "const_int_operand" " i, i") > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > - (any_float:VF > + (any_float:V_VLSF > (match_operand:<VNCONVERT> 3 "register_operand" " vr, vr")) > - (match_operand:VF 2 "vector_merge_operand" " vu, 0")))] > + (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0")))] > "TARGET_VECTOR" > "vfwcvt.f.x<u>.v\t%0,%3%p1" > [(set_attr "type" "vfwcvtitof") > @@ -7610,7 +7610,7 @@ > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (any_fix:<VNCONVERT> > - (match_operand:VF 3 "register_operand" " 0, 0, 0, 0, > vr, vr")) > + (match_operand:V_VLSF 3 "register_operand" " 0, 0, 0, 0, > vr, vr")) > (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, > vu, 0")))] > "TARGET_VECTOR" > "vfncvt.rtz.x<u>.f.w\t%0,%3%p1" > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-1.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-1.c > new file mode 100644 > index 00000000000..ca04f7f382e > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-1.c > @@ -0,0 +1,74 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 > --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ > + > +#include "def.h" > + > +DEF_CONVERT (fcvt, _Float16, int16_t, 4) > +DEF_CONVERT (fcvt, _Float16, int16_t, 16) > +DEF_CONVERT (fcvt, _Float16, int16_t, 32) > +DEF_CONVERT (fcvt, _Float16, int16_t, 64) > +DEF_CONVERT (fcvt, _Float16, int16_t, 128) > +DEF_CONVERT (fcvt, _Float16, int16_t, 256) > +DEF_CONVERT (fcvt, _Float16, int16_t, 512) > +DEF_CONVERT (fcvt, _Float16, int16_t, 1024) > +DEF_CONVERT (fcvt, _Float16, int16_t, 2048) > + > +DEF_CONVERT (fcvt, float, int32_t, 4) > +DEF_CONVERT (fcvt, float, int32_t, 16) > +DEF_CONVERT (fcvt, float, int32_t, 32) > +DEF_CONVERT (fcvt, float, int32_t, 64) > +DEF_CONVERT (fcvt, float, int32_t, 128) > +DEF_CONVERT (fcvt, float, int32_t, 256) > +DEF_CONVERT (fcvt, float, int32_t, 512) > +DEF_CONVERT (fcvt, float, int32_t, 1024) > + > +DEF_CONVERT (fcvt, double, int64_t, 4) > +DEF_CONVERT (fcvt, double, int64_t, 16) > +DEF_CONVERT (fcvt, double, int64_t, 32) > +DEF_CONVERT (fcvt, double, int64_t, 64) > +DEF_CONVERT (fcvt, double, int64_t, 128) > +DEF_CONVERT (fcvt, double, int64_t, 256) > +DEF_CONVERT (fcvt, double, int64_t, 512) > + > +DEF_CONVERT (fcvt, _Float16, uint16_t, 4) > +DEF_CONVERT (fcvt, _Float16, uint16_t, 16) > +DEF_CONVERT (fcvt, _Float16, uint16_t, 32) > +DEF_CONVERT (fcvt, _Float16, uint16_t, 64) > +DEF_CONVERT (fcvt, _Float16, uint16_t, 128) > +DEF_CONVERT (fcvt, _Float16, uint16_t, 256) > +DEF_CONVERT (fcvt, _Float16, uint16_t, 512) > +DEF_CONVERT (fcvt, _Float16, uint16_t, 1024) > +DEF_CONVERT (fcvt, _Float16, uint16_t, 2048) > + > +DEF_CONVERT (fcvt, float, uint32_t, 4) > +DEF_CONVERT (fcvt, float, uint32_t, 16) > +DEF_CONVERT (fcvt, float, uint32_t, 32) > +DEF_CONVERT (fcvt, float, uint32_t, 64) > +DEF_CONVERT (fcvt, float, uint32_t, 128) > +DEF_CONVERT (fcvt, float, uint32_t, 256) > +DEF_CONVERT (fcvt, float, uint32_t, 512) > +DEF_CONVERT (fcvt, float, uint32_t, 1024) > + > +DEF_CONVERT (fcvt, double, uint64_t, 4) > +DEF_CONVERT (fcvt, double, uint64_t, 16) > +DEF_CONVERT (fcvt, double, uint64_t, 32) > +DEF_CONVERT (fcvt, double, uint64_t, 64) > +DEF_CONVERT (fcvt, double, uint64_t, 128) > +DEF_CONVERT (fcvt, double, uint64_t, 256) > +DEF_CONVERT (fcvt, double, uint64_t, 512) > + > +/* { dg-final { scan-assembler-times {vfcvt\.rtz\.x\.f\.v} 24 } } */ > +/* { dg-final { scan-assembler-times {vfcvt\.rtz\.xu\.f\.v} 24 } } */ > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-10.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-10.c > new file mode 100644 > index 00000000000..95d04cd814c > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-10.c > @@ -0,0 +1,80 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 > --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ > + > +#include "def.h" > + > +DEF_CONVERT (fncvt, _Float16, int8_t, 4) > +DEF_CONVERT (fncvt, _Float16, int8_t, 16) > +DEF_CONVERT (fncvt, _Float16, int8_t, 32) > +DEF_CONVERT (fncvt, _Float16, int8_t, 64) > +DEF_CONVERT (fncvt, _Float16, int8_t, 128) > +DEF_CONVERT (fncvt, _Float16, int8_t, 256) > +DEF_CONVERT (fncvt, _Float16, int8_t, 512) > +DEF_CONVERT (fncvt, _Float16, int8_t, 1024) > +DEF_CONVERT (fncvt, _Float16, int8_t, 2048) > +DEF_CONVERT (fncvt, _Float16, int8_t, 4096) > + > +DEF_CONVERT (fncvt, _Float16, uint8_t, 4) > +DEF_CONVERT (fncvt, _Float16, uint8_t, 16) > +DEF_CONVERT (fncvt, _Float16, uint8_t, 32) > +DEF_CONVERT (fncvt, _Float16, uint8_t, 64) > +DEF_CONVERT (fncvt, _Float16, uint8_t, 128) > +DEF_CONVERT (fncvt, _Float16, uint8_t, 256) > +DEF_CONVERT (fncvt, _Float16, uint8_t, 512) > +DEF_CONVERT (fncvt, _Float16, uint8_t, 1024) > +DEF_CONVERT (fncvt, _Float16, uint8_t, 2048) > +DEF_CONVERT (fncvt, _Float16, uint8_t, 4096) > + > +DEF_CONVERT (fncvt, float, int16_t, 4) > +DEF_CONVERT (fncvt, float, int16_t, 16) > +DEF_CONVERT (fncvt, float, int16_t, 32) > +DEF_CONVERT (fncvt, float, int16_t, 64) > +DEF_CONVERT (fncvt, float, int16_t, 128) > +DEF_CONVERT (fncvt, float, int16_t, 256) > +DEF_CONVERT (fncvt, float, int16_t, 512) > +DEF_CONVERT (fncvt, float, int16_t, 1024) > +DEF_CONVERT (fncvt, float, int16_t, 2048) > + > +DEF_CONVERT (fncvt, float, uint16_t, 4) > +DEF_CONVERT (fncvt, float, uint16_t, 16) > +DEF_CONVERT (fncvt, float, uint16_t, 32) > +DEF_CONVERT (fncvt, float, uint16_t, 64) > +DEF_CONVERT (fncvt, float, uint16_t, 128) > +DEF_CONVERT (fncvt, float, uint16_t, 256) > +DEF_CONVERT (fncvt, float, uint16_t, 512) > +DEF_CONVERT (fncvt, float, uint16_t, 1024) > +DEF_CONVERT (fncvt, float, uint16_t, 2048) > + > +DEF_CONVERT (fncvt, double, int32_t, 4) > +DEF_CONVERT (fncvt, double, int32_t, 16) > +DEF_CONVERT (fncvt, double, int32_t, 32) > +DEF_CONVERT (fncvt, double, int32_t, 64) > +DEF_CONVERT (fncvt, double, int32_t, 128) > +DEF_CONVERT (fncvt, double, int32_t, 256) > +DEF_CONVERT (fncvt, double, int32_t, 512) > +DEF_CONVERT (fncvt, double, int32_t, 1024) > + > +DEF_CONVERT (fncvt, double, uint32_t, 4) > +DEF_CONVERT (fncvt, double, uint32_t, 16) > +DEF_CONVERT (fncvt, double, uint32_t, 32) > +DEF_CONVERT (fncvt, double, uint32_t, 64) > +DEF_CONVERT (fncvt, double, uint32_t, 128) > +DEF_CONVERT (fncvt, double, uint32_t, 256) > +DEF_CONVERT (fncvt, double, uint32_t, 512) > +DEF_CONVERT (fncvt, double, uint32_t, 1024) > + > +/* { dg-final { scan-assembler-times {vfncvt\.rtz\.x\.f\.w} 30 } } */ > +/* { dg-final { scan-assembler-times {vfncvt\.rtz\.xu\.f\.w} 30 } } */ > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-11.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-11.c > new file mode 100644 > index 00000000000..853acb3226b > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-11.c > @@ -0,0 +1,54 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 > --param=riscv-autovec-lmul=m8 -fno-trapping-math -fdump-tree-optimized" } */ > + > +#include "def.h" > + > +DEF_CONVERT (fncvt, float, int8_t, 4) > +DEF_CONVERT (fncvt, float, int8_t, 16) > +DEF_CONVERT (fncvt, float, int8_t, 32) > +DEF_CONVERT (fncvt, float, int8_t, 64) > +DEF_CONVERT (fncvt, float, int8_t, 128) > +DEF_CONVERT (fncvt, float, int8_t, 256) > +DEF_CONVERT (fncvt, float, int8_t, 512) > +DEF_CONVERT (fncvt, float, int8_t, 1024) > + > +DEF_CONVERT (fncvt, float, uint8_t, 4) > +DEF_CONVERT (fncvt, float, uint8_t, 16) > +DEF_CONVERT (fncvt, float, uint8_t, 32) > +DEF_CONVERT (fncvt, float, uint8_t, 64) > +DEF_CONVERT (fncvt, float, uint8_t, 128) > +DEF_CONVERT (fncvt, float, uint8_t, 256) > +DEF_CONVERT (fncvt, float, uint8_t, 512) > +DEF_CONVERT (fncvt, float, uint8_t, 1024) > + > +DEF_CONVERT (fncvt, double, int16_t, 4) > +DEF_CONVERT (fncvt, double, int16_t, 16) > +DEF_CONVERT (fncvt, double, int16_t, 32) > +DEF_CONVERT (fncvt, double, int16_t, 64) > +DEF_CONVERT (fncvt, double, int16_t, 128) > +DEF_CONVERT (fncvt, double, int16_t, 256) > +DEF_CONVERT (fncvt, double, int16_t, 512) > + > +DEF_CONVERT (fncvt, double, uint16_t, 4) > +DEF_CONVERT (fncvt, double, uint16_t, 16) > +DEF_CONVERT (fncvt, double, uint16_t, 32) > +DEF_CONVERT (fncvt, double, uint16_t, 64) > +DEF_CONVERT (fncvt, double, uint16_t, 128) > +DEF_CONVERT (fncvt, double, uint16_t, 256) > +DEF_CONVERT (fncvt, double, uint16_t, 512) > + > +/* { dg-final { scan-assembler-times {vfncvt\.rtz\.x\.f.w} 30 } } */ > +/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 30 } } */ > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-12.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-12.c > new file mode 100644 > index 00000000000..8fdfa447585 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-12.c > @@ -0,0 +1,36 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 > --param=riscv-autovec-lmul=m8 -fno-trapping-math -fdump-tree-optimized" } */ > + > +#include "def.h" > + > +DEF_CONVERT (fncvt, double, int8_t, 4) > +DEF_CONVERT (fncvt, double, int8_t, 16) > +DEF_CONVERT (fncvt, double, int8_t, 32) > +DEF_CONVERT (fncvt, double, int8_t, 64) > +DEF_CONVERT (fncvt, double, int8_t, 128) > +DEF_CONVERT (fncvt, double, int8_t, 256) > +DEF_CONVERT (fncvt, double, int8_t, 512) > + > +DEF_CONVERT (fncvt, double, uint8_t, 4) > +DEF_CONVERT (fncvt, double, uint8_t, 16) > +DEF_CONVERT (fncvt, double, uint8_t, 32) > +DEF_CONVERT (fncvt, double, uint8_t, 64) > +DEF_CONVERT (fncvt, double, uint8_t, 128) > +DEF_CONVERT (fncvt, double, uint8_t, 256) > +DEF_CONVERT (fncvt, double, uint8_t, 512) > + > +/* { dg-final { scan-assembler-times {vfncvt\.rtz\.x\.f.w} 14 } } */ > +/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 28 } } */ > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-2.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-2.c > new file mode 100644 > index 00000000000..4b6a168625c > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-2.c > @@ -0,0 +1,74 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 > --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ > + > +#include "def.h" > + > +DEF_CONVERT (fcvt, int16_t, _Float16, 4) > +DEF_CONVERT (fcvt, int16_t, _Float16, 16) > +DEF_CONVERT (fcvt, int16_t, _Float16, 32) > +DEF_CONVERT (fcvt, int16_t, _Float16, 64) > +DEF_CONVERT (fcvt, int16_t, _Float16, 128) > +DEF_CONVERT (fcvt, int16_t, _Float16, 256) > +DEF_CONVERT (fcvt, int16_t, _Float16, 512) > +DEF_CONVERT (fcvt, int16_t, _Float16, 1024) > +DEF_CONVERT (fcvt, int16_t, _Float16, 2048) > + > +DEF_CONVERT (fcvt, int32_t, float, 4) > +DEF_CONVERT (fcvt, int32_t, float, 16) > +DEF_CONVERT (fcvt, int32_t, float, 32) > +DEF_CONVERT (fcvt, int32_t, float, 64) > +DEF_CONVERT (fcvt, int32_t, float, 128) > +DEF_CONVERT (fcvt, int32_t, float, 256) > +DEF_CONVERT (fcvt, int32_t, float, 512) > +DEF_CONVERT (fcvt, int32_t, float, 1024) > + > +DEF_CONVERT (fcvt, int64_t, double, 4) > +DEF_CONVERT (fcvt, int64_t, double, 16) > +DEF_CONVERT (fcvt, int64_t, double, 32) > +DEF_CONVERT (fcvt, int64_t, double, 64) > +DEF_CONVERT (fcvt, int64_t, double, 128) > +DEF_CONVERT (fcvt, int64_t, double, 256) > +DEF_CONVERT (fcvt, int64_t, double, 512) > + > +DEF_CONVERT (fcvt, uint16_t, _Float16, 4) > +DEF_CONVERT (fcvt, uint16_t, _Float16, 16) > +DEF_CONVERT (fcvt, uint16_t, _Float16, 32) > +DEF_CONVERT (fcvt, uint16_t, _Float16, 64) > +DEF_CONVERT (fcvt, uint16_t, _Float16, 128) > +DEF_CONVERT (fcvt, uint16_t, _Float16, 256) > +DEF_CONVERT (fcvt, uint16_t, _Float16, 512) > +DEF_CONVERT (fcvt, uint16_t, _Float16, 1024) > +DEF_CONVERT (fcvt, uint16_t, _Float16, 2048) > + > +DEF_CONVERT (fcvt, uint32_t, float, 4) > +DEF_CONVERT (fcvt, uint32_t, float, 16) > +DEF_CONVERT (fcvt, uint32_t, float, 32) > +DEF_CONVERT (fcvt, uint32_t, float, 64) > +DEF_CONVERT (fcvt, uint32_t, float, 128) > +DEF_CONVERT (fcvt, uint32_t, float, 256) > +DEF_CONVERT (fcvt, uint32_t, float, 512) > +DEF_CONVERT (fcvt, uint32_t, float, 1024) > + > +DEF_CONVERT (fcvt, uint64_t, double, 4) > +DEF_CONVERT (fcvt, uint64_t, double, 16) > +DEF_CONVERT (fcvt, uint64_t, double, 32) > +DEF_CONVERT (fcvt, uint64_t, double, 64) > +DEF_CONVERT (fcvt, uint64_t, double, 128) > +DEF_CONVERT (fcvt, uint64_t, double, 256) > +DEF_CONVERT (fcvt, uint64_t, double, 512) > + > +/* { dg-final { scan-assembler-times {vfcvt\.f\.x\.v} 24 } } */ > +/* { dg-final { scan-assembler-times {vfcvt\.f\.xu\.v} 24 } } */ > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-3.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-3.c > new file mode 100644 > index 00000000000..6d74bdd35d4 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-3.c > @@ -0,0 +1,58 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 > --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ > + > +#include "def.h" > + > +DEF_CONVERT (fwcvt, _Float16, int32_t, 4) > +DEF_CONVERT (fwcvt, _Float16, int32_t, 16) > +DEF_CONVERT (fwcvt, _Float16, int32_t, 32) > +DEF_CONVERT (fwcvt, _Float16, int32_t, 64) > +DEF_CONVERT (fwcvt, _Float16, int32_t, 128) > +DEF_CONVERT (fwcvt, _Float16, int32_t, 256) > +DEF_CONVERT (fwcvt, _Float16, int32_t, 512) > +DEF_CONVERT (fwcvt, _Float16, int32_t, 1024) > +DEF_CONVERT (fwcvt, _Float16, int32_t, 2048) > + > +DEF_CONVERT (fwcvt, _Float16, uint32_t, 4) > +DEF_CONVERT (fwcvt, _Float16, uint32_t, 16) > +DEF_CONVERT (fwcvt, _Float16, uint32_t, 32) > +DEF_CONVERT (fwcvt, _Float16, uint32_t, 64) > +DEF_CONVERT (fwcvt, _Float16, uint32_t, 128) > +DEF_CONVERT (fwcvt, _Float16, uint32_t, 256) > +DEF_CONVERT (fwcvt, _Float16, uint32_t, 512) > +DEF_CONVERT (fwcvt, _Float16, uint32_t, 1024) > +DEF_CONVERT (fwcvt, _Float16, uint32_t, 2048) > + > +DEF_CONVERT (fwcvt, float, int64_t, 4) > +DEF_CONVERT (fwcvt, float, int64_t, 16) > +DEF_CONVERT (fwcvt, float, int64_t, 32) > +DEF_CONVERT (fwcvt, float, int64_t, 64) > +DEF_CONVERT (fwcvt, float, int64_t, 128) > +DEF_CONVERT (fwcvt, float, int64_t, 256) > +DEF_CONVERT (fwcvt, float, int64_t, 512) > +DEF_CONVERT (fwcvt, float, int64_t, 1024) > + > +DEF_CONVERT (fwcvt, float, uint64_t, 4) > +DEF_CONVERT (fwcvt, float, uint64_t, 16) > +DEF_CONVERT (fwcvt, float, uint64_t, 32) > +DEF_CONVERT (fwcvt, float, uint64_t, 64) > +DEF_CONVERT (fwcvt, float, uint64_t, 128) > +DEF_CONVERT (fwcvt, float, uint64_t, 256) > +DEF_CONVERT (fwcvt, float, uint64_t, 512) > +DEF_CONVERT (fwcvt, float, uint64_t, 1024) > + > +/* { dg-final { scan-assembler-times {vfwcvt\.rtz\.x\.f\.v} 19 } } */ > +/* { dg-final { scan-assembler-times {vfwcvt\.rtz\.xu\.f\.v} 19 } } */ > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-4.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-4.c > new file mode 100644 > index 00000000000..8ef991de44c > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-4.c > @@ -0,0 +1,36 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 > --param=riscv-autovec-lmul=m8 -fno-trapping-math -fdump-tree-optimized" } */ > + > +#include "def.h" > + > +DEF_CONVERT (fwcvt, _Float16, int64_t, 4) > +DEF_CONVERT (fwcvt, _Float16, int64_t, 16) > +DEF_CONVERT (fwcvt, _Float16, int64_t, 32) > +DEF_CONVERT (fwcvt, _Float16, int64_t, 64) > +DEF_CONVERT (fwcvt, _Float16, int64_t, 128) > +DEF_CONVERT (fwcvt, _Float16, int64_t, 256) > +DEF_CONVERT (fwcvt, _Float16, int64_t, 512) > + > +DEF_CONVERT (fwcvt, _Float16, uint64_t, 4) > +DEF_CONVERT (fwcvt, _Float16, uint64_t, 16) > +DEF_CONVERT (fwcvt, _Float16, uint64_t, 32) > +DEF_CONVERT (fwcvt, _Float16, uint64_t, 64) > +DEF_CONVERT (fwcvt, _Float16, uint64_t, 128) > +DEF_CONVERT (fwcvt, _Float16, uint64_t, 256) > +DEF_CONVERT (fwcvt, _Float16, uint64_t, 512) > + > +/* { dg-final { scan-assembler-times {vfwcvt\.rtz\.x\.f\.v} 14 } } */ > +/* { dg-final { scan-assembler-times {vsext\.vf2} 14 } } */ > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-5.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-5.c > new file mode 100644 > index 00000000000..09a44de616a > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-5.c > @@ -0,0 +1,80 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 > --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ > + > +#include "def.h" > + > +DEF_CONVERT (fwcvt, int8_t, _Float16, 4) > +DEF_CONVERT (fwcvt, int8_t, _Float16, 16) > +DEF_CONVERT (fwcvt, int8_t, _Float16, 32) > +DEF_CONVERT (fwcvt, int8_t, _Float16, 64) > +DEF_CONVERT (fwcvt, int8_t, _Float16, 128) > +DEF_CONVERT (fwcvt, int8_t, _Float16, 256) > +DEF_CONVERT (fwcvt, int8_t, _Float16, 512) > +DEF_CONVERT (fwcvt, int8_t, _Float16, 1024) > +DEF_CONVERT (fwcvt, int8_t, _Float16, 2048) > +DEF_CONVERT (fwcvt, int8_t, _Float16, 4096) > + > +DEF_CONVERT (fwcvt, uint8_t, _Float16, 4) > +DEF_CONVERT (fwcvt, uint8_t, _Float16, 16) > +DEF_CONVERT (fwcvt, uint8_t, _Float16, 32) > +DEF_CONVERT (fwcvt, uint8_t, _Float16, 64) > +DEF_CONVERT (fwcvt, uint8_t, _Float16, 128) > +DEF_CONVERT (fwcvt, uint8_t, _Float16, 256) > +DEF_CONVERT (fwcvt, uint8_t, _Float16, 512) > +DEF_CONVERT (fwcvt, uint8_t, _Float16, 1024) > +DEF_CONVERT (fwcvt, uint8_t, _Float16, 2048) > +DEF_CONVERT (fwcvt, uint8_t, _Float16, 4096) > + > +DEF_CONVERT (fwcvt, int16_t, float, 4) > +DEF_CONVERT (fwcvt, int16_t, float, 16) > +DEF_CONVERT (fwcvt, int16_t, float, 32) > +DEF_CONVERT (fwcvt, int16_t, float, 64) > +DEF_CONVERT (fwcvt, int16_t, float, 128) > +DEF_CONVERT (fwcvt, int16_t, float, 256) > +DEF_CONVERT (fwcvt, int16_t, float, 512) > +DEF_CONVERT (fwcvt, int16_t, float, 1024) > +DEF_CONVERT (fwcvt, int16_t, float, 2048) > + > +DEF_CONVERT (fwcvt, uint16_t, float, 4) > +DEF_CONVERT (fwcvt, uint16_t, float, 16) > +DEF_CONVERT (fwcvt, uint16_t, float, 32) > +DEF_CONVERT (fwcvt, uint16_t, float, 64) > +DEF_CONVERT (fwcvt, uint16_t, float, 128) > +DEF_CONVERT (fwcvt, uint16_t, float, 256) > +DEF_CONVERT (fwcvt, uint16_t, float, 512) > +DEF_CONVERT (fwcvt, uint16_t, float, 1024) > +DEF_CONVERT (fwcvt, uint16_t, float, 2048) > + > +DEF_CONVERT (fwcvt, int32_t, double, 4) > +DEF_CONVERT (fwcvt, int32_t, double, 16) > +DEF_CONVERT (fwcvt, int32_t, double, 32) > +DEF_CONVERT (fwcvt, int32_t, double, 64) > +DEF_CONVERT (fwcvt, int32_t, double, 128) > +DEF_CONVERT (fwcvt, int32_t, double, 256) > +DEF_CONVERT (fwcvt, int32_t, double, 512) > +DEF_CONVERT (fwcvt, int32_t, double, 1024) > + > +DEF_CONVERT (fwcvt, uint32_t, double, 4) > +DEF_CONVERT (fwcvt, uint32_t, double, 16) > +DEF_CONVERT (fwcvt, uint32_t, double, 32) > +DEF_CONVERT (fwcvt, uint32_t, double, 64) > +DEF_CONVERT (fwcvt, uint32_t, double, 128) > +DEF_CONVERT (fwcvt, uint32_t, double, 256) > +DEF_CONVERT (fwcvt, uint32_t, double, 512) > +DEF_CONVERT (fwcvt, uint32_t, double, 1024) > + > +/* { dg-final { scan-assembler-times {vfwcvt\.f\.x\.v} 30 } } */ > +/* { dg-final { scan-assembler-times {vfwcvt\.f\.xu\.v} 30 } } */ > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-6.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-6.c > new file mode 100644 > index 00000000000..2948dde0d0b > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-6.c > @@ -0,0 +1,55 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 > --param=riscv-autovec-lmul=m8 -fno-trapping-math -fdump-tree-optimized" } */ > + > +#include "def.h" > + > +DEF_CONVERT (fwcvt, int8_t, float, 4) > +DEF_CONVERT (fwcvt, int8_t, float, 16) > +DEF_CONVERT (fwcvt, int8_t, float, 32) > +DEF_CONVERT (fwcvt, int8_t, float, 64) > +DEF_CONVERT (fwcvt, int8_t, float, 128) > +DEF_CONVERT (fwcvt, int8_t, float, 256) > +DEF_CONVERT (fwcvt, int8_t, float, 512) > +DEF_CONVERT (fwcvt, int8_t, float, 1024) > + > +DEF_CONVERT (fwcvt, uint8_t, float, 4) > +DEF_CONVERT (fwcvt, uint8_t, float, 16) > +DEF_CONVERT (fwcvt, uint8_t, float, 32) > +DEF_CONVERT (fwcvt, uint8_t, float, 64) > +DEF_CONVERT (fwcvt, uint8_t, float, 128) > +DEF_CONVERT (fwcvt, uint8_t, float, 256) > +DEF_CONVERT (fwcvt, uint8_t, float, 512) > +DEF_CONVERT (fwcvt, uint8_t, float, 1024) > + > +DEF_CONVERT (fwcvt, int16_t, double, 4) > +DEF_CONVERT (fwcvt, int16_t, double, 16) > +DEF_CONVERT (fwcvt, int16_t, double, 32) > +DEF_CONVERT (fwcvt, int16_t, double, 64) > +DEF_CONVERT (fwcvt, int16_t, double, 128) > +DEF_CONVERT (fwcvt, int16_t, double, 256) > +DEF_CONVERT (fwcvt, int16_t, double, 512) > + > +DEF_CONVERT (fwcvt, uint16_t, double, 4) > +DEF_CONVERT (fwcvt, uint16_t, double, 16) > +DEF_CONVERT (fwcvt, uint16_t, double, 32) > +DEF_CONVERT (fwcvt, uint16_t, double, 64) > +DEF_CONVERT (fwcvt, uint16_t, double, 128) > +DEF_CONVERT (fwcvt, uint16_t, double, 256) > +DEF_CONVERT (fwcvt, uint16_t, double, 512) > + > +/* { dg-final { scan-assembler-times {vfwcvt\.f\.x\.v} 30 } } */ > +/* { dg-final { scan-assembler-times {vsext\.vf2} 15 } } */ > +/* { dg-final { scan-assembler-times {vzext\.vf2} 15 } } */ > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-7.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-7.c > new file mode 100644 > index 00000000000..ea39012b95a > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-7.c > @@ -0,0 +1,37 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 > --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ > + > +#include "def.h" > + > +DEF_CONVERT (fwcvt, int8_t, double, 4) > +DEF_CONVERT (fwcvt, int8_t, double, 16) > +DEF_CONVERT (fwcvt, int8_t, double, 32) > +DEF_CONVERT (fwcvt, int8_t, double, 64) > +DEF_CONVERT (fwcvt, int8_t, double, 128) > +DEF_CONVERT (fwcvt, int8_t, double, 256) > +DEF_CONVERT (fwcvt, int8_t, double, 512) > + > +DEF_CONVERT (fwcvt, uint8_t, double, 4) > +DEF_CONVERT (fwcvt, uint8_t, double, 16) > +DEF_CONVERT (fwcvt, uint8_t, double, 32) > +DEF_CONVERT (fwcvt, uint8_t, double, 64) > +DEF_CONVERT (fwcvt, uint8_t, double, 128) > +DEF_CONVERT (fwcvt, uint8_t, double, 256) > +DEF_CONVERT (fwcvt, uint8_t, double, 512) > + > +/* { dg-final { scan-assembler-times {vfwcvt\.f\.x\.v} 14 } } */ > +/* { dg-final { scan-assembler-times {vsext\.vf4} 7 } } */ > +/* { dg-final { scan-assembler-times {vzext\.vf4} 7 } } */ > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-8.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-8.c > new file mode 100644 > index 00000000000..59f36f582f6 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-8.c > @@ -0,0 +1,58 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 > --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ > + > +#include "def.h" > + > +DEF_CONVERT (fncvt, int32_t, _Float16, 4) > +DEF_CONVERT (fncvt, int32_t, _Float16, 16) > +DEF_CONVERT (fncvt, int32_t, _Float16, 32) > +DEF_CONVERT (fncvt, int32_t, _Float16, 64) > +DEF_CONVERT (fncvt, int32_t, _Float16, 128) > +DEF_CONVERT (fncvt, int32_t, _Float16, 256) > +DEF_CONVERT (fncvt, int32_t, _Float16, 512) > +DEF_CONVERT (fncvt, int32_t, _Float16, 1024) > +DEF_CONVERT (fncvt, int32_t, _Float16, 2048) > + > +DEF_CONVERT (fncvt, uint32_t, _Float16, 4) > +DEF_CONVERT (fncvt, uint32_t, _Float16, 16) > +DEF_CONVERT (fncvt, uint32_t, _Float16, 32) > +DEF_CONVERT (fncvt, uint32_t, _Float16, 64) > +DEF_CONVERT (fncvt, uint32_t, _Float16, 128) > +DEF_CONVERT (fncvt, uint32_t, _Float16, 256) > +DEF_CONVERT (fncvt, uint32_t, _Float16, 512) > +DEF_CONVERT (fncvt, uint32_t, _Float16, 1024) > +DEF_CONVERT (fncvt, uint32_t, _Float16, 2048) > + > +DEF_CONVERT (fncvt, int64_t, float, 4) > +DEF_CONVERT (fncvt, int64_t, float, 16) > +DEF_CONVERT (fncvt, int64_t, float, 32) > +DEF_CONVERT (fncvt, int64_t, float, 64) > +DEF_CONVERT (fncvt, int64_t, float, 128) > +DEF_CONVERT (fncvt, int64_t, float, 256) > +DEF_CONVERT (fncvt, int64_t, float, 512) > +DEF_CONVERT (fncvt, int64_t, float, 1024) > + > +DEF_CONVERT (fncvt, uint64_t, float, 4) > +DEF_CONVERT (fncvt, uint64_t, float, 16) > +DEF_CONVERT (fncvt, uint64_t, float, 32) > +DEF_CONVERT (fncvt, uint64_t, float, 64) > +DEF_CONVERT (fncvt, uint64_t, float, 128) > +DEF_CONVERT (fncvt, uint64_t, float, 256) > +DEF_CONVERT (fncvt, uint64_t, float, 512) > +DEF_CONVERT (fncvt, uint64_t, float, 1024) > + > +/* { dg-final { scan-assembler-times {vfncvt\.f\.x\.w} 19 } } */ > +/* { dg-final { scan-assembler-times {vfncvt\.f\.xu\.w} 19 } } */ > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-9.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-9.c > new file mode 100644 > index 00000000000..3546ddc4554 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-9.c > @@ -0,0 +1,22 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 > --param=riscv-autovec-lmul=m8 -fno-trapping-math -fdump-tree-optimized" } */ > + > +#include "def.h" > + > +DEF_CONVERT (fncvt, int64_t, _Float16, 4) > +DEF_CONVERT (fncvt, int64_t, _Float16, 16) > +DEF_CONVERT (fncvt, int64_t, _Float16, 32) > +DEF_CONVERT (fncvt, int64_t, _Float16, 64) > +DEF_CONVERT (fncvt, int64_t, _Float16, 128) > +DEF_CONVERT (fncvt, int64_t, _Float16, 256) > +DEF_CONVERT (fncvt, int64_t, _Float16, 512) > + > +DEF_CONVERT (fncvt, uint64_t, _Float16, 4) > +DEF_CONVERT (fncvt, uint64_t, _Float16, 16) > +DEF_CONVERT (fncvt, uint64_t, _Float16, 32) > +DEF_CONVERT (fncvt, uint64_t, _Float16, 64) > +DEF_CONVERT (fncvt, uint64_t, _Float16, 128) > +DEF_CONVERT (fncvt, uint64_t, _Float16, 256) > +DEF_CONVERT (fncvt, uint64_t, _Float16, 512) > + > +/* TODO: Currently, we can't vectorize this case. */
