+ vid sequence. The elt (i) can be either const_int or + const_poly_int. */ + HOST_WIDE_INT diff = rtx_to_poly_int64 (builder.elt (i)).to_constant () - i;
How about: poly_int64 diff = rtx_to_poly_int64 (builder.elt (i)) - i; rtx avl - = has_vl_op (insn->rtl ()) ? get_vl (insn->rtl ()) : dem.get_avl (); + = (has_vl_op (insn->rtl ()) && REG_P (get_vl (insn->rtl ()))) + ? get_vl (insn->rtl ()) + : dem.get_avl (); How about: rtx avl = dem.get_avl_or_vl_reg (); I wonder whether it is possible add a testcase for this issue ? juzhe.zh...@rivai.ai From: Li Xu Date: 2023-09-27 11:07 To: gcc-patches CC: kito.cheng; palmer; juzhe.zhong; xuli Subject: [PATCH] RISC-V: Bugfix for RTL check[PR111533] From: xuli <xu...@eswincomputing.com> Consider the flowing situation: BB5: local_dem(RVV Insn 1, AVL(reg zero)) RVV Insn 1: vmv.s.x, AVL (const_int 1) RVV Insn 2: vredsum.vs, AVL(reg zero) vmv.s.x has vl operand, the following code will get avl (cosnt_int) from RVV Insn 1. rtx avl = has_vl_op (insn->rtl ()) ? get_vl (insn->rtl ()) : dem.get_avl (); If use REGNO for const_int, the compiler will crash: during RTL pass: vsetvl res_debug.c: In function '__dn_count_labels': res_debug.c:1050:1: internal compiler error: RTL check: expected code 'reg', have 'const_int' in rhs_regno, at rtl.h:1934 1050 | } | ^ 0x8fb169 rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, int, char const*) ../.././gcc/gcc/rtl.cc:770 0x1399818 rhs_regno(rtx_def const*) ../.././gcc/gcc/rtl.h:1934 0x1399818 anticipatable_occurrence_p ../.././gcc/gcc/config/riscv/riscv-vsetvl.cc:348 So in this case avl should be obtained from dem. Another issue is caused by the following code: HOST_WIDE_INT diff = INTVAL (builder.elt (i)) - i; during RTL pass: expand ../../.././gcc/libgfortran/generated/matmul_c4.c: In function 'matmul_c4': ../../.././gcc/libgfortran/generated/matmul_c4.c:2906:39: internal compiler error: RTL check: expected code 'const_int', have 'const_poly_int' in expand_const_vector, at config/riscv/riscv-v.cc:1149 The builder.elt (i) can be either const_int or const_poly_int. PR target/111533 gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_const_vector): Fix bug. * config/riscv/riscv-vsetvl.cc (anticipatable_occurrence_p): Fix bug. --- gcc/config/riscv/riscv-v.cc | 6 ++++-- gcc/config/riscv/riscv-vsetvl.cc | 5 ++++- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 5f738634219..fb3c55b4705 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1147,8 +1147,10 @@ expand_const_vector (rtx target, rtx src) for (unsigned int i = 0; i < v.npatterns (); ++i) { /* Calculate the diff between the target sequence and - vid sequence. */ - HOST_WIDE_INT diff = INTVAL (builder.elt (i)) - i; + vid sequence. The elt (i) can be either const_int or + const_poly_int. */ + HOST_WIDE_INT diff = rtx_to_poly_int64 (builder.elt (i)).to_constant () - i; + v.quick_push (gen_int_mode (diff, v.inner_mode ())); } /* Step 2: Generate result = VID + diff. */ diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index 7af33e7ea6f..27000434341 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -308,7 +308,10 @@ anticipatable_occurrence_p (const bb_info *bb, const vector_insn_info dem) { /* rs1 (avl) are not modified in the basic block prior to the VSETVL. */ rtx avl - = has_vl_op (insn->rtl ()) ? get_vl (insn->rtl ()) : dem.get_avl (); + = (has_vl_op (insn->rtl ()) && REG_P (get_vl (insn->rtl ()))) + ? get_vl (insn->rtl ()) + : dem.get_avl (); + if (dem.dirty_p ()) { gcc_assert (!vsetvl_insn_p (insn->rtl ())); -- 2.17.1