From: Christoph Müllner <christoph.muell...@vrull.eu>
Fixes: c1bc7513b1d7 ("RISC-V: const: hide mvconst splitter from IRA")
A recent change broke the xtheadcondmov-indirect tests, because the order of
emitted instructions changed. Since the test is too strict when testing for
a fixed instruction order, let's change the tests to simply count instruction,
like it is done for similar tests.
Reported-by: Patrick O'Neill <patr...@rivosinc.com>
Signed-off-by: Christoph Müllner <christoph.muell...@vrull.eu>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xtheadcondmov-indirect.c: Make robust against
instruction reordering.
Signed-off-by: Christoph Müllner <christoph.muell...@vrull.eu>
---
.../gcc.target/riscv/xtheadcondmov-indirect.c | 89 ++++++-------------
1 file changed, 29 insertions(+), 60 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect.c
b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect.c
index c3253ba5239..427c9c1a41e 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect.c
@@ -1,16 +1,11 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_xtheadcondmov -fno-sched-pressure" { target {
rv32 } } } */
-/* { dg-options "-march=rv64gc_xtheadcondmov -fno-sched-pressure" { target {
rv64 } } } */
+/* { dg-options "-march=rv32gc_xtheadcondmov" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadcondmov" { target { rv64 } } } */
/* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
-/*
-** ConEmv_imm_imm_reg:
-** addi a[0-9]+,a[0-9]+,-1000
-** li a[0-9]+,10
-** th\.mvnez a[0-9]+,a[0-9]+,a[0-9]+
-** ret
-*/
+/* addi aX, aX, -1000
+ li aX, 10
+ th.mvnez aX, aX, aX */
int ConEmv_imm_imm_reg(int x, int y)
{
if (x == 1000)
@@ -18,13 +13,8 @@ int ConEmv_imm_imm_reg(int x, int y)
return y;
}
-/*
-** ConEmv_imm_reg_reg:
-** addi a[0-9]+,a[0-9]+,-1000
-** th.mveqz a[0-9]+,a[0-9]+,a[0-9]+
-** mv a[0-9]+,a[0-9]+
-** ret
-*/
+/* addi aX, aX, -1000
+ th.mveqz aX, aX, aX */
int ConEmv_imm_reg_reg(int x, int y, int z)
{
if (x == 1000)
@@ -32,13 +22,9 @@ int ConEmv_imm_reg_reg(int x, int y, int z)
return z;
}
-/*
-** ConEmv_reg_imm_reg:
-** sub a[0-9]+,a[0-9]+,a[0-9]+
-** li a[0-9]+,10
-** th.mvnez a[0-9]+,a[0-9]+,a[0-9]+
-** ret
-*/
+/* sub aX, aX, aX
+ li aX, 10
+ th.mvnez aX, aX, aX */
int ConEmv_reg_imm_reg(int x, int y, int z)
{
if (x == y)
@@ -46,13 +32,8 @@ int ConEmv_reg_imm_reg(int x, int y, int z)
return z;
}
-/*
-** ConEmv_reg_reg_reg:
-** sub a[0-9]+,a[0-9]+,a[0-9]+
-** th.mveqz a[0-9]+,a[0-9]+,a[0-9]+
-** mv a[0-9]+,a[0-9]+
-** ret
-*/
+/* sub aX, aX, aX
+ th.mveqz aX, aX, aX */
int ConEmv_reg_reg_reg(int x, int y, int z, int n)
{
if (x == y)
@@ -60,14 +41,10 @@ int ConEmv_reg_reg_reg(int x, int y, int z, int n)
return n;
}
-/*
-** ConNmv_imm_imm_reg:
-** addi a[0-9]+,a[0-9]+,-1000+
-** li a[0-9]+,9998336+
-** addi a[0-9]+,a[0-9]+,1664+
-** th.mveqz a[0-9]+,a[0-9]+,a[0-9]+
-** ret
-*/
+/* addi aX, aX, -1000
+ li aX, 9998336
+ addi aX, aX, 1664
+ th.mveqz aX, aX, aX */
int ConNmv_imm_imm_reg(int x, int y)
{
if (x != 1000)
@@ -75,13 +52,8 @@ int ConNmv_imm_imm_reg(int x, int y)
return y;
}
-/*
-**ConNmv_imm_reg_reg:
-** addi a[0-9]+,a[0-9]+,-1000+
-** th.mvnez a[0-9]+,a[0-9]+,a[0-9]+
-** mv a[0-9]+,a[0-9]+
-** ret
-*/
+/* addi aX, aX, 1000
+ th.mvnez aX, aX, aX */
int ConNmv_imm_reg_reg(int x, int y, int z)
{
if (x != 1000)
@@ -89,13 +61,9 @@ int ConNmv_imm_reg_reg(int x, int y, int z)
return z;
}
-/*
-**ConNmv_reg_imm_reg:
-** sub a[0-9]+,a[0-9]+,a[0-9]+
-** li a[0-9]+,10+
-** th.mveqz a[0-9]+,a[0-9]+,a[0-9]+
-** ret
-*/
+/* sub aX, aX, aX
+ li aX, 10
+ th.mveqz aX, aX, aX */
int ConNmv_reg_imm_reg(int x, int y, int z)
{
if (x != y)
@@ -103,16 +71,17 @@ int ConNmv_reg_imm_reg(int x, int y, int z)
return z;
}
-/*
-**ConNmv_reg_reg_reg:
-** sub a[0-9]+,a[0-9]+,a[0-9]+
-** th.mvnez a[0-9]+,a[0-9]+,a[0-9]+
-** mv a[0-9]+,a[0-9]+
-** ret
-*/
+/* sub aX, aX, aX
+ th.mvnez aX, aX, aX */
int ConNmv_reg_reg_reg(int x, int y, int z, int n)
{
if (x != y)
return z;
return n;
}
+
+/* { dg-final { scan-assembler-times "addi\t" 5 } } */
+/* { dg-final { scan-assembler-times "li\t" 4 } } */
+/* { dg-final { scan-assembler-times "sub\t" 4 } } */
+/* { dg-final { scan-assembler-times "th.mveqz\t" 4 } } */
+/* { dg-final { scan-assembler-times "th.mvnez\t" 4 } } */
--
2.41.0
