LGTM. Thanks.
juzhe.zh...@rivai.ai From: Li Xu Date: 2023-11-02 08:54 To: gcc-patches CC: kito.cheng; palmer; juzhe.zhong; xuli Subject: [PATCH] RISC-V: Support vcreate intrinsics for non-tuple types From: xuli <xu...@eswincomputing.com> https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/288 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc: Expand non-tuple intrinsics. * config/riscv/riscv-vector-builtins-functions.def (vcreate): Define non-tuple intrinsics. * config/riscv/riscv-vector-builtins-shapes.cc (struct vcreate_def): Ditto. * config/riscv/riscv-vector-builtins.cc: Add arg types. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/tuple_create.c: Rename to vcreate.c. * gcc.target/riscv/rvv/base/vcreate.c: New test. --- .../riscv/riscv-vector-builtins-bases.cc | 21 +- .../riscv/riscv-vector-builtins-functions.def | 6 + .../riscv/riscv-vector-builtins-shapes.cc | 25 +- gcc/config/riscv/riscv-vector-builtins.cc | 53 ++++ .../gcc.target/riscv/rvv/base/tuple_create.c | 123 --------- .../gcc.target/riscv/rvv/base/vcreate.c | 260 ++++++++++++++++++ 6 files changed, 357 insertions(+), 131 deletions(-) delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/tuple_create.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 0b1409a52e0..25ba31e2659 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -1798,6 +1798,10 @@ public: { unsigned int nargs = gimple_call_num_args (f.call); tree lhs_type = TREE_TYPE (f.lhs); + /* LMUL > 1 non-tuple vector types are not structure, + we can't use __val[index] to set the subpart. */ + if (!riscv_v_ext_tuple_mode_p (TYPE_MODE (lhs_type))) + return NULL; /* Replace the call with a clobber of the result (to prevent it from becoming upwards exposed) followed by stores into each individual @@ -1823,9 +1827,22 @@ public: return clobber; } - rtx expand (function_expander &) const override + rtx expand (function_expander &e) const override { - gcc_unreachable (); + if (!e.target) + return NULL_RTX; + gcc_assert (riscv_v_ext_vector_mode_p (GET_MODE (e.target))); + unsigned int nargs = call_expr_nargs (e.exp); + for (unsigned int i = 0; i < nargs; i++) + { + rtx src = expand_normal (CALL_EXPR_ARG (e.exp, i)); + poly_int64 offset = i * GET_MODE_SIZE (GET_MODE (src)); + rtx subreg = simplify_gen_subreg (GET_MODE (src), e.target, + GET_MODE (e.target), offset); + emit_move_insn (subreg, src); + } + + return e.target; } }; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index 911fd520195..1c37fd5fffe 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -617,6 +617,12 @@ DEF_RVV_FUNCTION (vget, vget, none_preds, all_v_vget_lmul1_x8_ops) DEF_RVV_FUNCTION (vget, vget, none_preds, all_v_vget_lmul2_x2_ops) DEF_RVV_FUNCTION (vget, vget, none_preds, all_v_vget_lmul2_x4_ops) DEF_RVV_FUNCTION (vget, vget, none_preds, all_v_vget_lmul4_x2_ops) +DEF_RVV_FUNCTION (vcreate, vcreate, none_preds, all_v_vcreate_lmul1_x2_ops) +DEF_RVV_FUNCTION (vcreate, vcreate, none_preds, all_v_vcreate_lmul1_x4_ops) +DEF_RVV_FUNCTION (vcreate, vcreate, none_preds, all_v_vcreate_lmul1_x8_ops) +DEF_RVV_FUNCTION (vcreate, vcreate, none_preds, all_v_vcreate_lmul2_x2_ops) +DEF_RVV_FUNCTION (vcreate, vcreate, none_preds, all_v_vcreate_lmul2_x4_ops) +DEF_RVV_FUNCTION (vcreate, vcreate, none_preds, all_v_vcreate_lmul4_x2_ops) // Tuple types DEF_RVV_FUNCTION (vset, vset, none_preds, all_v_vset_tuple_ops) diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc index 0bda934ae16..72b0d6a96a3 100644 --- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc @@ -728,13 +728,17 @@ struct vcreate_def : public build_base if (!return_type) continue; - machine_mode mode = TYPE_MODE (return_type); - unsigned int nf = get_nf (mode); + tree arg_type = function_instance.op_info->args[0].get_tree_type ( + function_instance.type.index); - for (unsigned int i = 0; i < nf; i++) - argument_types.quick_push ( - function_instance.op_info->args[0].get_tree_type ( - function_instance.type.index)); + machine_mode outer_mode = TYPE_MODE (return_type); + machine_mode inner_mode = TYPE_MODE (arg_type); + unsigned int nargs + = exact_div (GET_MODE_SIZE (outer_mode), GET_MODE_SIZE (inner_mode)) + .to_constant (); + + for (unsigned int i = 0; i < nargs; i++) + argument_types.quick_push (arg_type); b.add_unique_function (function_instance, (*group.shape), return_type, argument_types); @@ -748,6 +752,15 @@ struct vcreate_def : public build_base return nullptr; b.append_base_name (instance.base_name); b.append_name (operand_suffixes[instance.op_info->op]); + + if (instance.op_info->ret.base_type != RVV_BASE_vector) + { + vector_type_index arg_type_idx + = instance.op_info->args[0].get_function_type_index ( + instance.type.index); + b.append_name (type_suffixes[arg_type_idx].vector); + } + vector_type_index ret_type_idx = instance.op_info->ret.get_function_type_index (instance.type.index); b.append_name (type_suffixes[ret_type_idx].vector); diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index 2e33bf73549..650a1dc83bc 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -877,6 +877,11 @@ static CONSTEXPR const rvv_arg_type_info tuple_vset_args[] static CONSTEXPR const rvv_arg_type_info tuple_vcreate_args[] = {rvv_arg_type_info (RVV_BASE_tuple_subpart), rvv_arg_type_info_end}; +/* A list of args for vector_type func (vector_type) function. */ +static CONSTEXPR const rvv_arg_type_info ext_vcreate_args[] + = {rvv_arg_type_info (RVV_BASE_vector), + rvv_arg_type_info_end}; + /* A list of none preds that will be registered for intrinsic functions. */ static CONSTEXPR const predication_type_index none_preds[] = {PRED_TYPE_none, NUM_PRED_TYPES}; @@ -2517,6 +2522,54 @@ static CONSTEXPR const rvv_op_info all_none_void_tuple_ops rvv_arg_type_info (RVV_BASE_vector), /* Return type */ void_args /* Args */}; +/* A static operand information for vector_type func (vector_type) + * function registration. */ +static CONSTEXPR const rvv_op_info all_v_vcreate_lmul1_x2_ops + = {lmul1_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vlmul_ext_x2), /* Return type */ + ext_vcreate_args /* Args */}; + +/* A static operand information for vector_type func (vector_type) + * function registration. */ +static CONSTEXPR const rvv_op_info all_v_vcreate_lmul1_x4_ops + = {lmul1_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vlmul_ext_x4), /* Return type */ + ext_vcreate_args /* Args */}; + +/* A static operand information for vector_type func (vector_type) + * function registration. */ +static CONSTEXPR const rvv_op_info all_v_vcreate_lmul1_x8_ops + = {lmul1_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vlmul_ext_x8), /* Return type */ + ext_vcreate_args /* Args */}; + +/* A static operand information for vector_type func (vector_type) + * function registration. */ +static CONSTEXPR const rvv_op_info all_v_vcreate_lmul2_x2_ops + = {lmul2_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vlmul_ext_x2), /* Return type */ + ext_vcreate_args /* Args */}; + +/* A static operand information for vector_type func (vector_type) + * function registration. */ +static CONSTEXPR const rvv_op_info all_v_vcreate_lmul2_x4_ops + = {lmul2_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vlmul_ext_x4), /* Return type */ + ext_vcreate_args /* Args */}; + +/* A static operand information for vector_type func (vector_type) + * function registration. */ +static CONSTEXPR const rvv_op_info all_v_vcreate_lmul4_x2_ops + = {lmul4_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vlmul_ext_x2), /* Return type */ + ext_vcreate_args /* Args */}; + /* A list of all RVV base function types. */ static CONSTEXPR const function_type_info function_types[] = { #define DEF_RVV_TYPE_INDEX( \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/tuple_create.c b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple_create.c deleted file mode 100644 index b252b2f3cd4..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/tuple_create.c +++ /dev/null @@ -1,123 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */ - -#include "riscv_vector.h" - -vfloat16mf4x2_t test_vcreate_v_f16mf4x2(vfloat16mf4_t v0, vfloat16mf4_t v1) { - return __riscv_vcreate_v_f16mf4x2(v0, v1); -} - -vfloat16mf4x3_t test_vcreate_v_f16mf4x3(vfloat16mf4_t v0, vfloat16mf4_t v1, vfloat16mf4_t v2) { - return __riscv_vcreate_v_f16mf4x3(v0, v1, v2); -} - -vfloat16mf4x4_t test_vcreate_v_f16mf4x4(vfloat16mf4_t v0, vfloat16mf4_t v1, vfloat16mf4_t v2, vfloat16mf4_t v3) { - return __riscv_vcreate_v_f16mf4x4(v0, v1, v2, v3); -} - -vfloat16mf4x5_t test_vcreate_v_f16mf4x5(vfloat16mf4_t v0, vfloat16mf4_t v1, vfloat16mf4_t v2, vfloat16mf4_t v3, vfloat16mf4_t v4) { - return __riscv_vcreate_v_f16mf4x5(v0, v1, v2, v3, v4); -} - -vfloat16mf4x6_t test_vcreate_v_f16mf4x6(vfloat16mf4_t v0, vfloat16mf4_t v1, vfloat16mf4_t v2, vfloat16mf4_t v3, vfloat16mf4_t v4, vfloat16mf4_t v5) { - return __riscv_vcreate_v_f16mf4x6(v0, v1, v2, v3, v4, v5); -} - -vfloat16mf4x7_t test_vcreate_v_f16mf4x7(vfloat16mf4_t v0, vfloat16mf4_t v1, vfloat16mf4_t v2, vfloat16mf4_t v3, vfloat16mf4_t v4, vfloat16mf4_t v5, vfloat16mf4_t v6) { - return __riscv_vcreate_v_f16mf4x7(v0, v1, v2, v3, v4, v5, v6); -} - -vfloat16mf4x8_t test_vcreate_v_f16mf4x8(vfloat16mf4_t v0, vfloat16mf4_t v1, vfloat16mf4_t v2, vfloat16mf4_t v3, vfloat16mf4_t v4, vfloat16mf4_t v5, vfloat16mf4_t v6, vfloat16mf4_t v7) { - return __riscv_vcreate_v_f16mf4x8(v0, v1, v2, v3, v4, v5, v6, v7); -} - -vfloat32m1x2_t test_vcreate_v_f32m1x2(vfloat32m1_t v0, vfloat32m1_t v1) { - return __riscv_vcreate_v_f32m1x2(v0, v1); -} - -vfloat32m1x3_t test_vcreate_v_f32m1x3(vfloat32m1_t v0, vfloat32m1_t v1, vfloat32m1_t v2) { - return __riscv_vcreate_v_f32m1x3(v0, v1, v2); -} - -vfloat32m1x4_t test_vcreate_v_f32m1x4(vfloat32m1_t v0, vfloat32m1_t v1, vfloat32m1_t v2, vfloat32m1_t v3) { - return __riscv_vcreate_v_f32m1x4(v0, v1, v2, v3); -} - -vfloat32m1x5_t test_vcreate_v_f32m1x5(vfloat32m1_t v0, vfloat32m1_t v1, vfloat32m1_t v2, vfloat32m1_t v3, vfloat32m1_t v4) { - return __riscv_vcreate_v_f32m1x5(v0, v1, v2, v3, v4); -} - -vfloat32m1x6_t test_vcreate_v_f32m1x6(vfloat32m1_t v0, vfloat32m1_t v1, vfloat32m1_t v2, vfloat32m1_t v3, vfloat32m1_t v4, vfloat32m1_t v5) { - return __riscv_vcreate_v_f32m1x6(v0, v1, v2, v3, v4, v5); -} - -vfloat32m1x7_t test_vcreate_v_f32m1x7(vfloat32m1_t v0, vfloat32m1_t v1, vfloat32m1_t v2, vfloat32m1_t v3, vfloat32m1_t v4, vfloat32m1_t v5, vfloat32m1_t v6) { - return __riscv_vcreate_v_f32m1x7(v0, v1, v2, v3, v4, v5, v6); -} - -vfloat32m1x8_t test_vcreate_v_f32m1x8(vfloat32m1_t v0, vfloat32m1_t v1, vfloat32m1_t v2, vfloat32m1_t v3, vfloat32m1_t v4, vfloat32m1_t v5, vfloat32m1_t v6, vfloat32m1_t v7) { - return __riscv_vcreate_v_f32m1x8(v0, v1, v2, v3, v4, v5, v6, v7); -} - -vfloat64m2x2_t test_vcreate_v_f64m2x2(vfloat64m2_t v0, vfloat64m2_t v1) { - return __riscv_vcreate_v_f64m2x2(v0, v1); -} - -vfloat64m2x3_t test_vcreate_v_f64m2x3(vfloat64m2_t v0, vfloat64m2_t v1, vfloat64m2_t v2) { - return __riscv_vcreate_v_f64m2x3(v0, v1, v2); -} - -vfloat64m2x4_t test_vcreate_v_f64m2x4(vfloat64m2_t v0, vfloat64m2_t v1, vfloat64m2_t v2, vfloat64m2_t v3) { - return __riscv_vcreate_v_f64m2x4(v0, v1, v2, v3); -} - -vfloat64m4x2_t test_vcreate_v_f64m4x2(vfloat64m4_t v0, vfloat64m4_t v1) { - return __riscv_vcreate_v_f64m4x2(v0, v1); -} - -vint8m2x2_t test_vcreate_v_i8m2x2(vint8m2_t v0, vint8m2_t v1) { - return __riscv_vcreate_v_i8m2x2(v0, v1); -} - -vint8m2x3_t test_vcreate_v_i8m2x3(vint8m2_t v0, vint8m2_t v1, vint8m2_t v2) { - return __riscv_vcreate_v_i8m2x3(v0, v1, v2); -} - -vint8m2x4_t test_vcreate_v_i8m2x4(vint8m2_t v0, vint8m2_t v1, vint8m2_t v2, vint8m2_t v3) { - return __riscv_vcreate_v_i8m2x4(v0, v1, v2, v3); -} - -vint8m4x2_t test_vcreate_v_i8m4x2(vint8m4_t v0, vint8m4_t v1) { - return __riscv_vcreate_v_i8m4x2(v0, v1); -} - -vint16m4x2_t test_vcreate_v_i16m4x2(vint16m4_t v0, vint16m4_t v1) { - return __riscv_vcreate_v_i16m4x2(v0, v1); -} - -vint32m4x2_t test_vcreate_v_i32m4x2(vint32m4_t v0, vint32m4_t v1) { - return __riscv_vcreate_v_i32m4x2(v0, v1); -} - -vint64m2x2_t test_vcreate_v_i64m2x2(vint64m2_t v0, vint64m2_t v1) { - return __riscv_vcreate_v_i64m2x2(v0, v1); -} - -vint64m2x3_t test_vcreate_v_i64m2x3(vint64m2_t v0, vint64m2_t v1, vint64m2_t v2) { - return __riscv_vcreate_v_i64m2x3(v0, v1, v2); -} - -vint64m2x4_t test_vcreate_v_i64m2x4(vint64m2_t v0, vint64m2_t v1, vint64m2_t v2, vint64m2_t v3) { - return __riscv_vcreate_v_i64m2x4(v0, v1, v2, v3); -} - -/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 7 } } */ -/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 35 } } */ -/* { dg-final { scan-assembler-times {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 35 } } */ -/* { dg-final { scan-assembler-times {vl2re8\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 9 } } */ -/* { dg-final { scan-assembler-times {vl1re32\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 35 } } */ -/* { dg-final { scan-assembler-times {vl2re64\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 18 } } */ -/* { dg-final { scan-assembler-times {vl4re64\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 2 } } */ -/* { dg-final { scan-assembler-times {vs1r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 35 } } */ -/* { dg-final { scan-assembler-times {vs2r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 27 } } */ -/* { dg-final { scan-assembler-times {vs4r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c new file mode 100644 index 00000000000..158eec04e22 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c @@ -0,0 +1,260 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +vfloat16m2_t +test_vcreate_v_f16m1_f16m2 (vfloat16m1_t v0, vfloat16m1_t v1) +{ + return __riscv_vcreate_v_f16m1_f16m2 (v0, v1); +} + +vfloat32m2_t +test_vcreate_v_f32m1_f32m2 (vfloat32m1_t v0, vfloat32m1_t v1) +{ + return __riscv_vcreate_v_f32m1_f32m2 (v0, v1); +} + +vfloat64m4_t +test_vcreate_v_f64m1_f64m4 (vfloat64m1_t v0, vfloat64m1_t v1, vfloat64m1_t v2, + vfloat64m1_t v3) +{ + return __riscv_vcreate_v_f64m1_f64m4 (v0, v1, v2, v3); +} + +vint8m2_t +test_vcreate_v_i8m1_i8m2 (vint8m1_t v0, vint8m1_t v1) +{ + return __riscv_vcreate_v_i8m1_i8m2 (v0, v1); +} + +vint16m8_t +test_vcreate_v_i16m1_i16m8 (vint16m1_t v0, vint16m1_t v1, vint16m1_t v2, + vint16m1_t v3, vint16m1_t v4, vint16m1_t v5, + vint16m1_t v6, vint16m1_t v7) +{ + return __riscv_vcreate_v_i16m1_i16m8 (v0, v1, v2, v3, v4, v5, v6, v7); +} + +vint32m4_t +test_vcreate_v_i32m2_i32m4 (vint32m2_t v0, vint32m2_t v1) +{ + return __riscv_vcreate_v_i32m2_i32m4 (v0, v1); +} + +vint64m8_t +test_vcreate_v_i64m2_i64m8 (vint64m2_t v0, vint64m2_t v1, vint64m2_t v2, + vint64m2_t v3) +{ + return __riscv_vcreate_v_i64m2_i64m8 (v0, v1, v2, v3); +} + +vuint8m2_t +test_vcreate_v_u8m1_u8m2 (vuint8m1_t v0, vuint8m1_t v1) +{ + return __riscv_vcreate_v_u8m1_u8m2 (v0, v1); +} + +vuint16m8_t +test_vcreate_v_u16m1_u16m8 (vuint16m1_t v0, vuint16m1_t v1, vuint16m1_t v2, + vuint16m1_t v3, vuint16m1_t v4, vuint16m1_t v5, + vuint16m1_t v6, vuint16m1_t v7) +{ + return __riscv_vcreate_v_u16m1_u16m8 (v0, v1, v2, v3, v4, v5, v6, v7); +} + +vuint32m8_t +test_vcreate_v_u32m2_u32m8 (vuint32m2_t v0, vuint32m2_t v1, vuint32m2_t v2, + vuint32m2_t v3) +{ + return __riscv_vcreate_v_u32m2_u32m8 (v0, v1, v2, v3); +} + +vuint64m4_t +test_vcreate_v_u64m2_u64m4 (vuint64m2_t v0, vuint64m2_t v1) +{ + return __riscv_vcreate_v_u64m2_u64m4 (v0, v1); +} + +vfloat16mf4x2_t +test_vcreate_v_f16mf4x2 (vfloat16mf4_t v0, vfloat16mf4_t v1) +{ + return __riscv_vcreate_v_f16mf4x2 (v0, v1); +} + +vfloat16mf4x3_t +test_vcreate_v_f16mf4x3 (vfloat16mf4_t v0, vfloat16mf4_t v1, vfloat16mf4_t v2) +{ + return __riscv_vcreate_v_f16mf4x3 (v0, v1, v2); +} + +vfloat16mf4x4_t +test_vcreate_v_f16mf4x4 (vfloat16mf4_t v0, vfloat16mf4_t v1, vfloat16mf4_t v2, + vfloat16mf4_t v3) +{ + return __riscv_vcreate_v_f16mf4x4 (v0, v1, v2, v3); +} + +vfloat16mf4x5_t +test_vcreate_v_f16mf4x5 (vfloat16mf4_t v0, vfloat16mf4_t v1, vfloat16mf4_t v2, + vfloat16mf4_t v3, vfloat16mf4_t v4) +{ + return __riscv_vcreate_v_f16mf4x5 (v0, v1, v2, v3, v4); +} + +vfloat16mf4x6_t +test_vcreate_v_f16mf4x6 (vfloat16mf4_t v0, vfloat16mf4_t v1, vfloat16mf4_t v2, + vfloat16mf4_t v3, vfloat16mf4_t v4, vfloat16mf4_t v5) +{ + return __riscv_vcreate_v_f16mf4x6 (v0, v1, v2, v3, v4, v5); +} + +vfloat16mf4x7_t +test_vcreate_v_f16mf4x7 (vfloat16mf4_t v0, vfloat16mf4_t v1, vfloat16mf4_t v2, + vfloat16mf4_t v3, vfloat16mf4_t v4, vfloat16mf4_t v5, + vfloat16mf4_t v6) +{ + return __riscv_vcreate_v_f16mf4x7 (v0, v1, v2, v3, v4, v5, v6); +} + +vfloat16mf4x8_t +test_vcreate_v_f16mf4x8 (vfloat16mf4_t v0, vfloat16mf4_t v1, vfloat16mf4_t v2, + vfloat16mf4_t v3, vfloat16mf4_t v4, vfloat16mf4_t v5, + vfloat16mf4_t v6, vfloat16mf4_t v7) +{ + return __riscv_vcreate_v_f16mf4x8 (v0, v1, v2, v3, v4, v5, v6, v7); +} + +vfloat32m1x2_t +test_vcreate_v_f32m1x2 (vfloat32m1_t v0, vfloat32m1_t v1) +{ + return __riscv_vcreate_v_f32m1x2 (v0, v1); +} + +vfloat32m1x3_t +test_vcreate_v_f32m1x3 (vfloat32m1_t v0, vfloat32m1_t v1, vfloat32m1_t v2) +{ + return __riscv_vcreate_v_f32m1x3 (v0, v1, v2); +} + +vfloat32m1x4_t +test_vcreate_v_f32m1x4 (vfloat32m1_t v0, vfloat32m1_t v1, vfloat32m1_t v2, + vfloat32m1_t v3) +{ + return __riscv_vcreate_v_f32m1x4 (v0, v1, v2, v3); +} + +vfloat32m1x5_t +test_vcreate_v_f32m1x5 (vfloat32m1_t v0, vfloat32m1_t v1, vfloat32m1_t v2, + vfloat32m1_t v3, vfloat32m1_t v4) +{ + return __riscv_vcreate_v_f32m1x5 (v0, v1, v2, v3, v4); +} + +vfloat32m1x6_t +test_vcreate_v_f32m1x6 (vfloat32m1_t v0, vfloat32m1_t v1, vfloat32m1_t v2, + vfloat32m1_t v3, vfloat32m1_t v4, vfloat32m1_t v5) +{ + return __riscv_vcreate_v_f32m1x6 (v0, v1, v2, v3, v4, v5); +} + +vfloat32m1x7_t +test_vcreate_v_f32m1x7 (vfloat32m1_t v0, vfloat32m1_t v1, vfloat32m1_t v2, + vfloat32m1_t v3, vfloat32m1_t v4, vfloat32m1_t v5, + vfloat32m1_t v6) +{ + return __riscv_vcreate_v_f32m1x7 (v0, v1, v2, v3, v4, v5, v6); +} + +vfloat32m1x8_t +test_vcreate_v_f32m1x8 (vfloat32m1_t v0, vfloat32m1_t v1, vfloat32m1_t v2, + vfloat32m1_t v3, vfloat32m1_t v4, vfloat32m1_t v5, + vfloat32m1_t v6, vfloat32m1_t v7) +{ + return __riscv_vcreate_v_f32m1x8 (v0, v1, v2, v3, v4, v5, v6, v7); +} + +vfloat64m2x2_t +test_vcreate_v_f64m2x2 (vfloat64m2_t v0, vfloat64m2_t v1) +{ + return __riscv_vcreate_v_f64m2x2 (v0, v1); +} + +vfloat64m2x3_t +test_vcreate_v_f64m2x3 (vfloat64m2_t v0, vfloat64m2_t v1, vfloat64m2_t v2) +{ + return __riscv_vcreate_v_f64m2x3 (v0, v1, v2); +} + +vfloat64m2x4_t +test_vcreate_v_f64m2x4 (vfloat64m2_t v0, vfloat64m2_t v1, vfloat64m2_t v2, + vfloat64m2_t v3) +{ + return __riscv_vcreate_v_f64m2x4 (v0, v1, v2, v3); +} + +vfloat64m4x2_t +test_vcreate_v_f64m4x2 (vfloat64m4_t v0, vfloat64m4_t v1) +{ + return __riscv_vcreate_v_f64m4x2 (v0, v1); +} + +vint8m2x2_t +test_vcreate_v_i8m2x2 (vint8m2_t v0, vint8m2_t v1) +{ + return __riscv_vcreate_v_i8m2x2 (v0, v1); +} + +vint8m2x3_t +test_vcreate_v_i8m2x3 (vint8m2_t v0, vint8m2_t v1, vint8m2_t v2) +{ + return __riscv_vcreate_v_i8m2x3 (v0, v1, v2); +} + +vint8m2x4_t +test_vcreate_v_i8m2x4 (vint8m2_t v0, vint8m2_t v1, vint8m2_t v2, vint8m2_t v3) +{ + return __riscv_vcreate_v_i8m2x4 (v0, v1, v2, v3); +} + +vint8m4x2_t +test_vcreate_v_i8m4x2 (vint8m4_t v0, vint8m4_t v1) +{ + return __riscv_vcreate_v_i8m4x2 (v0, v1); +} + +vint16m4x2_t +test_vcreate_v_i16m4x2 (vint16m4_t v0, vint16m4_t v1) +{ + return __riscv_vcreate_v_i16m4x2 (v0, v1); +} + +vint32m4x2_t +test_vcreate_v_i32m4x2 (vint32m4_t v0, vint32m4_t v1) +{ + return __riscv_vcreate_v_i32m4x2 (v0, v1); +} + +vint64m2x2_t +test_vcreate_v_i64m2x2 (vint64m2_t v0, vint64m2_t v1) +{ + return __riscv_vcreate_v_i64m2x2 (v0, v1); +} + +vint64m2x3_t +test_vcreate_v_i64m2x3 (vint64m2_t v0, vint64m2_t v1, vint64m2_t v2) +{ + return __riscv_vcreate_v_i64m2x3 (v0, v1, v2); +} + +vint64m2x4_t +test_vcreate_v_i64m2x4 (vint64m2_t v0, vint64m2_t v1, vint64m2_t v2, + vint64m2_t v3) +{ + return __riscv_vcreate_v_i64m2x4 (v0, v1, v2, v3); +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 7 } } */ +/* { dg-final { scan-assembler-times {v[ls]e16\.v\s+v[0-9]+,\s*0\([0-9a-x]+\)} 70 } } */ +/* { dg-final { scan-assembler-times {vl[0-9]+re[0-9]+\.v\s+v[0-9]+,\s*0\([0-9a-x]+\)} 110 } } */ +/* { dg-final { scan-assembler-times {vs[0-9]+r\.v\s+v[0-9]+,\s*0\([a-x0-9]+\)} 81 } } */ -- 2.17.1
