The pattern "*extend<SHORT:mode><SUPERQI:mode>2_bitmanip" and
"*zero_extendhi<GPR:mode>2_bitmanip" in bitmanip.md are similar
to the pattern "*th_memidx_bb_extendqi<SUPERQI:mode>2" and
"*th_memidx_bb_zero_extendhi<GPR:mode>2" in thead.md, which will
cause the wrong instruction to be generated and report the
following error in binutils:
Assembler messages:
Error: illegal operands `lb a5,(a0),1,0'
In fact, the correct instruction is "th.lbia a5,(a0),1,0".
gcc/ChangeLog:
* config/riscv/bitmanip.md: Avoid the conflict between
zbb and xtheadmemidx in patterns.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xtheadfmemidx-uindex-zbb.c: New test.
---
gcc/config/riscv/bitmanip.md | 4 +--
.../riscv/xtheadfmemidx-uindex-zbb.c | 30 +++++++++++++++++++
2 files changed, 32 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-zbb.c
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index a9c8275fca7..878395c3ffa 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -290,7 +290,7 @@ (define_insn "*<bitmanip_optab>di2"
(define_insn "*zero_extendhi<GPR:mode>2_bitmanip"
[(set (match_operand:GPR 0 "register_operand" "=r,r")
(zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
- "TARGET_ZBB"
+ "TARGET_ZBB && !TARGET_XTHEADMEMIDX"
"@
zext.h\t%0,%1
lhu\t%0,%1"
@@ -301,7 +301,7 @@ (define_insn "*extend<SHORT:mode><SUPERQI:mode>2_bitmanip"
[(set (match_operand:SUPERQI 0 "register_operand" "=r,r")
(sign_extend:SUPERQI
(match_operand:SHORT 1 "nonimmediate_operand" " r,m")))]
- "TARGET_ZBB"
+ "TARGET_ZBB && !TARGET_XTHEADMEMIDX"
"@
sext.<SHORT:size>\t%0,%1
l<SHORT:size>\t%0,%1"
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-zbb.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-zbb.c
new file mode 100644
index 00000000000..a05bc220cba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-zbb.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */
+/* { dg-options "-march=rv64gc_zbb_xtheadmemidx -mabi=lp64d" { target { rv64 }
} } */
+/* { dg-options "-march=rv32imafc_zbb_xtheadmemidx -mabi=ilp32f" { target {
rv32 } } } */
+
+const unsigned char *
+read_uleb128(const unsigned char *p, unsigned long *val)
+{
+ unsigned int shift = 0;
+ unsigned char byte;
+ unsigned long result;
+
+ result = 0;
+ do
+ {
+ byte = *p++;
+ result |= ((unsigned long)byte & 0x7f) << shift;
+ shift += 7;
+ } while (byte & 0x80);
+
+ *val = result;
+ return p;
+}
+
+void test(const unsigned char *p, unsigned long utmp)
+{
+ p = read_uleb128(p, &utmp);
+}
+
+/* { dg-final { scan-assembler-not {\mlb\ta[0-9],\(a[0-9]\),1,0\M} } } */
base-commit: 04d8a47608dcae7f61805e3566e3a1571b574405
--
2.17.1
