> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 6a2009ffb05..08bbb657a06 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -374,10 +374,24 @@ void
> emit_vlmax_insn_lra (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl)
> {
> gcc_assert (!can_create_pseudo_p ());
> + machine_mode mode = GET_MODE (ops[0]);
>
> - insn_expander<RVV_INSN_OPERANDS_MAX> e (insn_flags, true);
> - e.set_vl (vl);
> - e.emit_insn ((enum insn_code) icode, ops);
> + if (imm_avl_p (mode))
> + {
> + /* Even though VL is a real hardreg already allocated since
> + it is post-RA now, we still gain benefits that we emit
> + vsetivli zero, imm instead of vsetvli VL, zero which is
> + we can be more flexible in post-RA instruction scheduling. */
> + insn_expander<RVV_INSN_OPERANDS_MAX> e (insn_flags, false);
> + e.set_vl (gen_int_mode (GET_MODE_NUNITS (mode), Pmode));
> + e.emit_insn ((enum insn_code) icode, ops);
> + }
> + else
> + {
> + insn_expander<RVV_INSN_OPERANDS_MAX> e (insn_flags, true);
> + e.set_vl (vl);
> + e.emit_insn ((enum insn_code) icode, ops);
> + }
It's a separate optimization which should not be included within this patch.
> }
>
> /* Emit an RVV insn with a predefined vector length. Contrary to
> @@ -2148,6 +2162,7 @@ expand_tuple_move (rtx *ops)
> offset = ops[2];
> }
>
> + emit_vlmax_vsetvl (subpart_mode, ops[4]);
I didn't get why we need vlmax vsetvl here?
We use code_for_pred_mov if subpart_mode is fractional LMUL mode
and will use the whole reg load store if not fractional LMUL.
So we don't need explicitly vsetvl for the above 2 cases in my understanding?
I know I must miss something, do you mind giving me a few more explanations?
> if (MEM_P (ops[1]))
> {
> /* Load operations. */
