On 11/17/23 04:39, juzhe.zh...@rivai.ai wrote:
90% theadvector extension reusing current RVV 1.0 instructions patterns:
Just change ASM, For example:
@@ -2923,7 +2923,7 @@ (define_insn "*pred_mulh<v_su><mode>_scalar"
(match_operand:VFULLI_D 3 "register_operand" "vr,vr, vr, vr")]
VMULH)
(match_operand:VFULLI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
"TARGET_VECTOR"
- "vmulh<v_su>.vx\t%0,%3,%z4%p1"
+ "%^vmulh<v_su>.vx\t%0,%3,%z4%p1"
[(set_attr "type" "vimul")
(set_attr "mode" "<MODE>")])
+ if (letter == '^')
+ {
+ if (TARGET_XTHEADVECTOR)
+ fputs ("th.", file);
+ return;
+ }
I assume this hunk is meant for riscv_output_operand in riscv.cc. We
may also need to add '^' to the punct_valid_p hook. But yes, this is
the preferred way to go when all we need to do is prefix the instruction
with "th.".
Btw, stage 1 will close soon. So I will review this patch on GCC-15 as
long as all other RISC-V maintainers agree.
I *think* it's a gcc-15 issue. Philipp T. and I briefly spoke about
this at the RVI summit a couple weeks back and he indicated the thead
vector work was targeting gcc-15.
Jeff
