"juzhe.zh...@rivai.ai" <juzhe.zh...@rivai.ai> writes: > Hi, Richard. > > Here is an example for vsext.vf2. > > The general pattern for this instruction as follows: > > (set (operand 0) (unspec:...(operand 1))) > > We have a TARGET_MIN_VLEN macro which specify minimum VLEN according to -march > > Consider this case V16QI -> V16HI of vsext.vf2 > > > When TARGET_MIN_VLEN == 128 > The constraint for vsext.vf should be: > > (set (operand 0: V16HI "=vr,&vr") (unspec:...(operand 1: V16QI "register > filter1, vr"))) > > Wheras when TARGET_MIN_VLEN > 128, > We are expecting the constraint: > (set (operand 0: V16HI "=&vr") (unspec:...(operand 1: V16QI "vr"))) > > That is, same mode, same instruction pattern. We want the constraint to be > different according to TARGET_MIN_VLEN. > > Currently, I don't know whether we can have an approach to support this > feature.
It looks like TARGET_MIN_VLEN == 128 provides an extra alternative on top of what TARGET_MIN_VLEN > 128 provides. Is that right? If so, the usual way to do that is to provide both alternatives, and use the "enabled" attribute to restrict the first alternative to TARGET_MIN_VLEN == 128. Thanks, Richard
