Rename lasx_xvfrsqrt*/lsx_vfrsqrt* to rsqrt<mode>2 to align with standard pattern name.
gcc/ChangeLog: * config/loongarch/lasx.md (lasx_xvfrsqrt_<flasxfmt>): Renamed to .. (*rsqrt<mode>2): .. this. * config/loongarch/loongarch-builtins.cc (CODE_FOR_lsx_vfrsqrt_d): Redefine to standard pattern name. (CODE_FOR_lsx_vfrsqrt_s): Ditto. (CODE_FOR_lasx_xvfrsqrt_d): Ditto. (CODE_FOR_lasx_xvfrsqrt_s): Ditto. * config/loongarch/loongarch.md (*rsqrt<mode>a): Remove. (*rsqrt<mode>2): New insn pattern. (*rsqrt<mode>b): Remove. * config/loongarch/lsx.md (lsx_vfrsqrt_<flsxfmt>): Renamed to .. (*rsqrt<mode>2): .. this. diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md index dd60d2bfed3..5f78cc45ccd 100644 --- a/gcc/config/loongarch/lasx.md +++ b/gcc/config/loongarch/lasx.md @@ -1710,10 +1710,10 @@ (define_insn "lasx_xvfrint_<flasxfmt>" [(set_attr "type" "simd_fcvt") (set_attr "mode" "<MODE>")]) -(define_insn "lasx_xvfrsqrt_<flasxfmt>" +(define_insn "rsqrt<mode>2" [(set (match_operand:FLASX 0 "register_operand" "=f") - (unspec:FLASX [(match_operand:FLASX 1 "register_operand" "f")] - UNSPEC_LASX_XVFRSQRT))] + (unspec:FLASX [(match_operand:FLASX 1 "register_operand" "f")] + UNSPEC_LASX_XVFRSQRT))] "ISA_HAS_LASX" "xvfrsqrt.<flasxfmt>\t%u0,%u1" [(set_attr "type" "simd_fdiv") diff --git a/gcc/config/loongarch/loongarch-builtins.cc b/gcc/config/loongarch/loongarch-builtins.cc index 47f658d6ab5..43d853bc961 100644 --- a/gcc/config/loongarch/loongarch-builtins.cc +++ b/gcc/config/loongarch/loongarch-builtins.cc @@ -473,6 +473,8 @@ AVAIL_ALL (lasx, ISA_HAS_LASX) #define CODE_FOR_lsx_vssrlrn_bu_h CODE_FOR_lsx_vssrlrn_u_bu_h #define CODE_FOR_lsx_vssrlrn_hu_w CODE_FOR_lsx_vssrlrn_u_hu_w #define CODE_FOR_lsx_vssrlrn_wu_d CODE_FOR_lsx_vssrlrn_u_wu_d +#define CODE_FOR_lsx_vfrsqrt_d CODE_FOR_rsqrtv2df2 +#define CODE_FOR_lsx_vfrsqrt_s CODE_FOR_rsqrtv4sf2 /* LoongArch ASX define CODE_FOR_lasx_mxxx */ #define CODE_FOR_lasx_xvsadd_b CODE_FOR_ssaddv32qi3 @@ -743,6 +745,8 @@ AVAIL_ALL (lasx, ISA_HAS_LASX) #define CODE_FOR_lasx_xvsat_hu CODE_FOR_lasx_xvsat_u_hu #define CODE_FOR_lasx_xvsat_wu CODE_FOR_lasx_xvsat_u_wu #define CODE_FOR_lasx_xvsat_du CODE_FOR_lasx_xvsat_u_du +#define CODE_FOR_lasx_xvfrsqrt_d CODE_FOR_rsqrtv4df2 +#define CODE_FOR_lasx_xvfrsqrt_s CODE_FOR_rsqrtv8sf2 static const struct loongarch_builtin_description loongarch_builtins[] = { #define LARCH_MOVFCSR2GR 0 diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 7b09926d1a7..0b6910d84ab 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -60,6 +60,7 @@ (define_c_enum "unspec" [ UNSPEC_TIE ;; RSQRT + UNSPEC_RSQRT UNSPEC_RSQRTE ;; RECIP @@ -1137,25 +1138,14 @@ (define_insn "sqrt<mode>2" (set_attr "mode" "<UNITMODE>") (set_attr "insn_count" "1")]) -(define_insn "*rsqrt<mode>a" +(define_insn "*rsqrt<mode>2" [(set (match_operand:ANYF 0 "register_operand" "=f") - (div:ANYF (match_operand:ANYF 1 "const_1_operand" "") - (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))] - "flag_unsafe_math_optimizations" - "frsqrt.<fmt>\t%0,%2" - [(set_attr "type" "frsqrt") - (set_attr "mode" "<UNITMODE>") - (set_attr "insn_count" "1")]) - -(define_insn "*rsqrt<mode>b" - [(set (match_operand:ANYF 0 "register_operand" "=f") - (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "") - (match_operand:ANYF 2 "register_operand" "f"))))] - "flag_unsafe_math_optimizations" - "frsqrt.<fmt>\t%0,%2" + (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")] + UNSPEC_RSQRT))] + "TARGET_HARD_FLOAT" + "frsqrt.<fmt>\t%0,%1" [(set_attr "type" "frsqrt") - (set_attr "mode" "<UNITMODE>") - (set_attr "insn_count" "1")]) + (set_attr "mode" "<UNITMODE>")]) ;; Approximate Reciprocal Square Root Instructions. diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md index 391e84f8d1d..130d77e164b 100644 --- a/gcc/config/loongarch/lsx.md +++ b/gcc/config/loongarch/lsx.md @@ -1638,10 +1638,10 @@ (define_insn "lsx_vfrint_<flsxfmt>" [(set_attr "type" "simd_fcvt") (set_attr "mode" "<MODE>")]) -(define_insn "lsx_vfrsqrt_<flsxfmt>" +(define_insn "rsqrt<mode>2" [(set (match_operand:FLSX 0 "register_operand" "=f") - (unspec:FLSX [(match_operand:FLSX 1 "register_operand" "f")] - UNSPEC_LSX_VFRSQRT))] + (unspec:FLSX [(match_operand:FLSX 1 "register_operand" "f")] + UNSPEC_LSX_VFRSQRT))] "ISA_HAS_LSX" "vfrsqrt.<flsxfmt>\t%w0,%w1" [(set_attr "type" "simd_fdiv") -- 2.20.1