On Tue, Dec 5, 2023 at 3:29 AM Hongyu Wang <hongyu.w...@intel.com> wrote: > > From: Kong Lingling <lingling.k...@intel.com> > > Legacy adc patterns are commonly adopted to TImode add, when extending TImode > add to NDD version, operands[0] and operands[1] can be different, so extra > move > should be emitted if those patterns have optimization when adding const0_rtx. > > NDD instructions will automatically zero-extend dest register to 64bit, so for > zext patterns it can adopt all NDD form that have memory src input. > > gcc/ChangeLog: > > * config/i386/i386.md (*add<dwi>3_doubleword): Add ndd constraints, > and > move operands[1] to operands[0] when they are not equal. > (*add<dwi>3_doubleword_cc_overflow_1): Likewise. > (*add<dwi>3_doubleword_zext): Add ndd constraints. > (*addv<dwi>4_doubleword): Likewise. > (*addv<dwi>4_doubleword_1): Likewise. > (addv<mode>4_overflow_1): Likewise. > (*addv<mode>4_overflow_2): Likewise. > (@add<mode>3_carry): Likewise. > (*add<mode>3_carry_0): Likewise. > (*addsi3_carry_zext): Likewise. > (addcarry<mode>): Likewise. > (addcarry<mode>_0): Likewise. > (*addcarry<mode>_1): Likewise. > (*add<mode>3_eq): Likewise. > (*add<mode>3_ne): Likewise. > (*addsi3_carry_zext_0): Likewise, and use nonimmediate_operand for > operands[1] to accept memory input for NDD alternative. > > gcc/testsuite/ChangeLog: > > * gcc.target/i386/apx-ndd-adc.c: New test. > --- > gcc/config/i386/i386.md | 191 ++++++++++++-------- > gcc/testsuite/gcc.target/i386/apx-ndd-adc.c | 15 ++ > 2 files changed, 134 insertions(+), 72 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/i386/apx-ndd-adc.c > > diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md > index 6b316e698bb..358a3857f89 100644 > --- a/gcc/config/i386/i386.md > +++ b/gcc/config/i386/i386.md > @@ -6291,12 +6291,12 @@ (define_expand "add<mode>3" > TARGET_APX_NDD); DONE;") > > (define_insn_and_split "*add<dwi>3_doubleword" > - [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro,r") > + [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro,r,r,r") > (plus:<DWI> > - (match_operand:<DWI> 1 "nonimmediate_operand" "%0,0") > - (match_operand:<DWI> 2 "x86_64_hilo_general_operand" "r<di>,o"))) > + (match_operand:<DWI> 1 "nonimmediate_operand" "%0,0,ro,r") > + (match_operand:<DWI> 2 "x86_64_hilo_general_operand" > "r<di>,o,r<di>,r"))) > (clobber (reg:CC FLAGS_REG))]
If we relax the requirement for TImode register pair, then =&r output should be used here (and in other TImode instructions) for apx_ndd ISA. Uros.
